What is known—and still unconfirmed—about Alphabet’s reported collaboration with AMD on a 10th generation Tensor Processing Unit, including the report’s source and lack of public confirmation, the TPU’s likely focus on reinforcement learning and agentic AI workloads requiring hig

The AMD–Google TPU v10 project is a credible but unverified report—not an announced program. The reported strategic logic is plausible: a more CPU-heavy, tightly integrated accelerator for reinforcement learning and agentic workloads, but neither company has confirmed the design, commercial terms, volume, or timing.

• Origin and status of the report. The claim originated in a SemiAnalysis client note described as “market chatter,” then was reported by Tom’s Hardware and others. It says Google may be working with AMD on a tenth-generation TPU; it does not establish that a finalized product, supply agreement, or production commitment exists.

• What the purported design would target. The hypothesis is a hybrid TPU with AMD x86 CPU cores integrated on the accelerator package. Reinforcement learning, reasoning, robotics, and agentic systems involve orchestration, environment simulation, tool use, branching, and control logic that can raise the needed CPU-to-accelerator ratio relative to conventional dense LLM training. Google’s TPU 8i systems reportedly use one Axion CPU per two TPUs, versus one CPU per four TPUs in seventh-generation TPU systems—an indicative, not definitive, sign of this shift.

• Why AMD is technically relevant. AMD could contribute x86 CPU IP and advanced multi-die/3D packaging expertise. Its MI300A is the closest proof point: it combines Zen CPU cores and GPU chiplets in one package with unified memory, demonstrating the sort of CPU–accelerated-compute integration that the reported TPU concept would require. The TPU would still be Google’s custom ASIC, not an MI300A derivative.

• Potential business importance for AMD. If real, this would expand AMD beyond selling standard EPYC CPUs and Instinct GPUs into custom AI ASIC development for a hyperscaler. A successful Google design win could also validate AMD as a supplier of CPU IP, packaging, interconnect, and integration services for other large cloud customers’ bespoke silicon programs. This remains upside speculation until Google or AMD confirms orders and economics.

• Google’s TPU supplier landscape. Broadcom remains an established Google custom-chip partner, and reports have also linked MediaTek to later TPU work. The Marvell agreement is confirmed by an SEC filing; the AMD and MediaTek roles should be treated as reported rather than confirmed unless the companies disclose them.

• The confirmed Marvell agreement matters more immediately. Marvell disclosed that Google signed a July 29 commercial agreement for custom semiconductor products tied to the TPU ecosystem, including AI inference accelerators and storage, network, memory-interface, and near-memory-compute products. On August 18, Marvell issued Google a warrant for up to 58,970,907 shares at $206.58 per share—about $12.2 billion at full exercise—with vesting tied to qualifying purchases through Marvell’s fiscal 2033.

• Strategic implication: multisourcing. Taken together, Broadcom’s ongoing role, Marvell’s disclosed deal, the reported MediaTek engagement, and the AMD rumor suggest Google is building optionality across a broader TPU supply chain. That can improve bargaining power, access to scarce engineering and packaging capacity, and resilience—but it does not necessarily mean Broadcom has lost its central position.

• Market reaction. Marvell shares rose sharply after the disclosure, while Broadcom sold off, reflecting concern that Google could diversify custom-silicon spending. Some market commentary interprets the deal primarily as evidence that the total custom-AI-chip market is expanding, rather than as a zero-sum transfer from Broadcom; on that view, a broadcom selloff based solely on the Marvell news may be excessive. The strength of that conclusion is uncertain because no supplier allocations or order values were disclosed.

• Why TPU v10 would likely be years away. There is no published roadmap, tape-out date, or launch schedule for a TPU v10. A tenth-generation platform implies multiple intervening design cycles, and a new CPU-on-package architecture would require IP integration, physical design, packaging qualification, software enablement, and hyperscale deployment validation. It should therefore be viewed as a multi-year possibility, not a near-term revenue event for AMD.