Google Is Reportedly Putting CPU Cores Inside Its Next TPU — And That Changes Everything for Agentic AI

Context matters. Broadcom remains Google's long-standing TPU co-design partner, with a disclosed five-year cooperation agreement signed in March 2026 covering generations v8 through v11 . MediaTek handles I/O and manufacturing coordination for the current Ironwood (TPU v7x) generation . The AMD involvement appears to be a project within the v10 generation — not necessarily a full replacement of Broadcom, though Broadcom's Ironwood CoWoS output was reportedly revised downward by approximately 32,000 wafers .

Separately, Google is reportedly considering Samsung Foundry for component production of the v10 (codenamed "Ice Fish") to diversify beyond TSMC , and has been in late-stage talks with Marvell for other custom AI chips .

Key caveat: Nothing is confirmed by Google or AMD. The SemiAnalysis report is market chatter, not an official announcement, and the AMD project may be a specific SKU, an experimental path, or a diversification hedge .

Why Hybrid Chips Make Sense for Agentic AI and Reinforcement Learning

The move from a pure-matrix ASIC toward a hybrid chip with integrated CPU cores is a direct architectural response to the changing nature of AI workloads — particularly reinforcement learning (RL) and agentic AI.

Agentic AI Is CPU-Bound, Not GPU-Bound

Traditional batch inference is almost entirely GPU-bound: a prompt goes in, the GPU runs a forward pass, tokens come back . Agentic AI workloads are fundamentally different. Orchestration, planning, tool calling, sandbox execution, and environment interaction all run on CPUs, not GPUs .

An academic study found that tool-dominated agentic AI workloads are significantly bottlenecked by tool processing on the CPU, consuming up to 88% of end-to-end latency . A separate analysis by Akash Borate put the number even higher, at up to 90.6% .

The CPU:GPU Ratio Is Shifting Radically

In AI training clusters, the CPU-to-GPU ratio is roughly 1:7 or 1:8 . As workloads shift to inference, that drops to 1:3 or 1:4 . For agentic deployments, Intel disclosed in its Q1 2026 earnings call that some customers are already running four CPUs per GPU — a 1:1 ratio in certain clusters .

Morgan Stanley projects $32.5–$60 billion in incremental CPU market growth by 2030, driven entirely by this shift . AMD itself has argued that agentic AI is not a single GPU-centric inference workload but a heterogeneous end-to-end workflow requiring high core density and high thread count CPUs for orchestration and sandbox execution .

Reinforcement Learning Demands Tight Sandbox Loops

RL training — especially for agentic models — requires repeated cycles of sandbox execution, environment simulation, reward computation, and policy updates. These loops involve substantial CPU-side orchestration that does not map efficiently to pure matrix accelerators.

Nvidia's Vera (88-core Olympus design) and Intel's Xeon 6+ are both being optimized for this "tight reinforcement learning sandbox loop" pattern . The hardware industry is converging on a shared insight: future AI accelerators will not be pure matrix engines.

Google's Hybrid TPU v10 as a Leading Indicator

By integrating AMD CPU cores directly on the TPU package, Google could eliminate PCIe bottlenecks for these CPU-heavy agentic loops, reduce latency, and handle the "tool call → environment step → update policy" cycle on a single tightly coupled die. This is the hardware embodiment of the insight that future AI systems will be heterogeneous system-on-package designs that mix compute types based on workload phase.

The Broader Implications

The Bottom Line

Google reportedly putting CPU cores inside its TPU v10 is not an incremental tweak — it is a recognition that the AI accelerator of 2028 will look very different from the one of 2024. Agentic AI and reinforcement learning are rewriting the rules of compute architecture, and the chip that handles a tool-calling loop a thousand times a second needs to be built differently from the chip that does one giant matrix multiply.

If the SemiAnalysis chatter is right, Google and AMD are building that chip right now.