The AI Chip Bottleneck Nobody Is Talking About

Who Is Hoarding All the Capacity?

More than 85% of total CoWoS capacity has already been pre-allocated to just four groups: Nvidia, Broadcom, AMD, and hyperscalers such as AWS, Google, and Meta .

• Nvidia alone is projected to book ~595,000 CoWoS wafers in 2026, accounting for roughly 60% of total global demand . Of that, 510,000 wafers are allocated to CoWoS-L technology for its next-generation Rubin AI chips and Vera CPUs .
• Broadcom — which counts Google's TPU, Meta, and OpenAI as clients — accounts for approximately 15% of 2026 allocations .
• TSMC's internal growth rate is slowing to just 26% year-over-year by 2026 as it shifts more volume to OSAT partners, even as total global CoWoS-like capacity grows 48% to 1.313 million wafers annually .

OSAT Partners: ASE and Amkor Take the Overflow

TSMC cannot build enough internal CoWoS lines fast enough. Its solution is to outsource the back-end Wafer-on-Substrate (WoS) portion of CoWoS to outsourced semiconductor assembly and test (OSAT) partners. The critical nuance: OSATs handle only the less complex substrate-assembly and final-test stage, not the full CoWoS process. The front-end chip-on-wafer (CoW) step stays with TSMC .

• ASE Group and SPIL are already working with TSMC on the CoWoS-S oS process. By 2025, ASE was expected to handle 40–50% of TSMC's outsourced CoWoS-S oS packaging, and ASE's new Kaohsiung K28 facility, slated for completion in 2026, will add further capacity .
• Amkor Technology is also receiving outsourced CoWoS work. Combined OSAT (ASE, Amkor, SPIL) monthly capacity was expected to exceed 40,000 wafers by the end of 2025 .
• By the end of 2026, TrendForce estimates total industry CoWoS capacity at ~200k wpm, with TSMC running ~120k wpm internally and ASE/Amkor soaking up ~80k wpm as overflow .
• A major expansion of outsourced CoW processes is planned starting in the second half of 2026 .
• Mizuho recently raised TSMC's monthly CoWoS capacity forecast to 140,000 units by 2026 and 190,000–200,000 by 2027, citing surging AI server CPU demand .

The OSAT role is being redefined from a downstream afterthought into an integral extension of the foundry value chain — but it is a partial fix. The most complex packaging steps remain TSMC-only.

MediaTek's Historic Pivot: Dual-Sourcing with Intel EMIB-T

The most strategic response to the CoWoS crunch comes from MediaTek, which has publicly confirmed it supports both TSMC's CoWoS and Intel's EMIB advanced packaging technologies for its AI ASIC designs, letting customers choose between them . This is the first time a major fabless customer has publicly split its advanced-packaging orders between the two foundries for a single product family — and it is volume procurement, not a technology evaluation .

The First-Gen ASIC: Intel EMIB-T Goes Live in Q4 2026

MediaTek's first custom data-center AI ASIC enters volume production in Q4 2026 and adopts Intel's EMIB-T advanced packaging . The chip was designed for an unnamed US cloud service provider — reported by analysts to be Google, designing a tensor processing unit .

• During a May 2026 press briefing, MediaTek SVP Vince Hu said: "We are among the select few custom silicon manufacturers that accommodate both TSMC's CoWoS and Intel's EMIB. Our customers have the flexibility to choose" .
• The motivation is pragmatic: a client reportedly chose Intel's EMIB partly for cost and capacity availability — both increasingly scarce at TSMC .

$5 Billion War Chest and a 26% Market Share Target

MediaTek is doubling down. Its board has approved $5 billion in financing to secure supply chain capacity and fuel expansion from AI ASIC chips to full-scale systems and platforms . The company expects its data-center AI chip business to generate more than $2 billion in revenue in 2026 and targets a 26% share of the AI ASIC market by 2028 .

Critical Distinction: Not a Replacement, a Diversification

MediaTek's first-gen ASIC uses Intel EMIB-T specifically . But the company is simultaneously developing designs for both TSMC CoWoS and Intel EMIB. It is not replacing one with the other — it is giving customers a choice in a supply-constrained world. Intel's EMIB is projected to enable larger package scalability (8–12x reticle size by 2026–2027, versus CoWoS-S's roughly 3.3x), but TrendForce notes that EMIB's limited bridge area and routing density can constrain bandwidth versus CoWoS, making it better suited for ASICs than GPUs .

Why Advanced Packaging Became the Primary AI Chip Bottleneck

CoWoS packaging has overtaken leading-edge wafer fabrication as the single biggest constraint on AI chip supply. The numbers tell the story:

Overall advanced packaging capacity is forecast to grow roughly 80% from 2022 to 2027 . But even that dramatic expansion is not keeping pace with AI demand. JPMorgan forecasts total industry CoWoS consumption reaching 1.15 million wafers in 2026 and 1.55 million in 2027, meaning non-TSMC sources (OSATs) will have to absorb an order-of-magnitude increase in volumes .

Intel's EMIB-T is the primary CoWoS competitor gaining real traction, but analysts caution it remains better suited to ASIC designs than to the highest-bandwidth GPU applications. The real story may be that the advanced packaging bottleneck is not a temporary crunch — it is a structural shift that is forcing the entire AI chip industry to diversify its packaging supply chain for the first time.