Why MediaTek Chose Intel's EMIB-T Over TSMC's CoWoS for Its Next-Gen AI Chip

The advanced packaging battleground for next-generation AI chips has a surprising new front. In a dramatic strategic pivot revealed at COMPUTEX 2026, Taiwanese chip design giant MediaTek announced its next-generation chip will exclusively use Intel's EMIB-T technology, abandoning TSMC's dominant CoWoS for this specific project . This decision not only validates Intel's long-promised foundry ambitions but also signals a potential fracturing of the near-monopoly TSMC has held on cutting-edge AI chip assembly.

The move is a calculated gambit by MediaTek, which is rapidly expanding into the custom AI ASIC market. By betting on Intel's nascent but promising technology, MediaTek gains a critical second packaging lane to bypass the severe capacity crunch at TSMC, where CoWoS allocation is fiercely contested by titans like NVIDIA and AMD . The deal is project-specific, not a wholesale defection, and MediaTek continues to use TSMC for its flagship smartphone SoCs . Nevertheless, it represents the most significant crack in TSMC's advanced packaging armor to date.

A Colossal Win for Intel Foundry's Credibility

For Intel Foundry, this is a watershed moment. Winning a flagship design from MediaTek—a historically TSMC-loyal powerhouse—is powerful external validation that its EMIB-T technology is not just a slideware alternative but a production-viable option for complex AI accelerators. Intel CFO Dave Zinsner recently stated that the company is "close to closing some deals that are in the billions per year in terms of revenue" on advanced packaging alone, with EMIB-T as the primary growth driver .

This commitment is crucial because it addresses a chronic weakness in Intel's foundry narrative: a lack of high-profile third-party success stories. With MediaTek on board, EMIB-T is transformed from a technical curiosity into a credible commercial offering, giving other hyperscalers and chip designers the confidence to diversify their supply chains away from TSMC's oversubscribed CoWoS capacity .

EMIB-T vs. CoWoS: A Technical Fork in the Road

The choice between Intel's EMIB-T and TSMC's CoWoS is a fundamental architectural decision that impacts cost, scalability, and power delivery. The core difference lies in how they connect multiple compute dies and high-bandwidth memory (HBM) stacks.

TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) uses a large, passive silicon interposer as a foundation upon which all chips are placed. This full-size interposer acts as an ultra-dense data highway with thousands of vertical connections (TSVs), offering extremely high bandwidth but at a very high cost . The size of this interposer is bounded by the lithography reticle limit, which constrains the maximum package size and can negatively impact yields as complexity grows .

Intel’s EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Vias) takes a fundamentally different approach. Instead of a monolithic interposer, it embeds tiny, localized silicon bridges directly into the organic package substrate only at the exact points where high-speed connections are needed between specific dies . This eliminates the expensive full-size silicon slab, reducing material cost and enabling physically larger packages—up to a massive 120×180 mm, capable of integrating over 38 bridge dies and more than 12 reticle-sized compute chiplets—because the package isn't limited by a single interposer’s reticle .

A key upgrade in EMIB-T over Intel’s legacy EMIB is the introduction of through-silicon vias (TSVs) inside the bridges. While legacy EMIB routes signals around the bridge, EMIB-T routes them through it, dramatically improving signal integrity and power delivery by reducing resistance by more than 30% compared to the old cantilever power supply path . The technology also integrates high-power MIM capacitors, making it better suited for the power delivery demands of HBM4-class memory .

In summary, CoWoS prioritizes maximum bandwidth via a unified, high-cost interposer, while EMIB-T offers a more modular, potentially cheaper, and massively scalable architecture at the cost of ecosystem maturity and proven production yields.

The Timeline: From Tape-Out to Production

MediaTek's commitment has a concrete, aggressive timeline. The company disclosed that the project is targeting tape-out in Q4 2026, with mass production commencing in Q4 2027 . This schedule aligns with Intel's own roadmap, which calls for EMIB-T to enter a full production fab rollout this year, with the broader EMIB technology expected to begin a meaningful revenue ramp in the second half of 2026 . The tape-out in late 2026 serves as the critical design-freeze moment, after which the long and risky path to achieving high-volume manufacturing yields begins.

The Analyst's Warning: Kuo's Concerns on the Yield Gap

This ambitious schedule is shadowed by a major technical risk: yield. Renowned analyst Ming-Chi Kuo has emerged as a prominent voice of caution, warning that the transition from validation to mass production will be exceptionally difficult.

According to disclosures, Intel’s EMIB-T process has achieved a technology validation yield of approximately 90% on Google's next-generation TPU, code-named "Humufish," which is also targeted for the second half of 2027 . While Kuo describes hitting 90% as a "very positive but reasonable data point" for a technology still under development, he stresses that it falls "significantly short" of the ~98% yield target considered necessary for commercially viable mass production .

Crucially, Kuo draws a sharp distinction between validation yield and true mass-production yield, noting that with some of the product specifications for Humufish still unfinalized, the 90% figure represents limited validation data rather than a reliable production forecast . His most pointed warning is that getting from 90% to 98% is harder than getting from project kickoff to 90% . This final stretch is where intricate interactions between design, process, and materials create a torturous optimization landscape. A Citibank research report reinforces this cautious view, noting that due to its mature and dominant ecosystem, TSMC faces minimal near-term competitive pressure from Intel .

The Secretive Google Connection

Adding complexity to the story is the widely reported but officially unconfirmed partnership between MediaTek and Google. Supply-chain sources consistently report that MediaTek is designing custom AI ASICs, including a tensor processing unit (TPU), for a major data center client—strongly believed to be Google . The 90% EMIB-T validation yield was achieved specifically on Google's next-generation TPU, code-named "Humufish" .

However, MediaTek has publicly declined to identify Google as a customer and refused to comment on whether it will use EMIB technology for Google's chips . This ambiguity makes MediaTek's exclusive EMIB-T commitment even more significant: it suggests that at least one major customer was convinced enough by Intel’s packaging roadmap to greenlight a project on it, a decision that reportedly comes down to the cost and capacity benefits of EMIB over a maxed-out CoWoS .

A Shift in Stance, Not a Defection

The exclusive EMIB-T commitment is a dramatic strategic pivot. Just days before the COMPUTEX announcement, MediaTek's public posture was one of a neutral dual-source provider. Senior Vice President Vince Hu stated, “We’re one of the few custom silicon providers that support both (TSMC’s) CoWoS and (Intel’s) EMIB. We let our customers choose” .

The leap from a neutral position to an exclusive, project-specific commitment signals confidence but also the intense pressure to secure capacity. Ultimately, the decision appears to be a practical one, not a total divorce. MediaTek continues its deep relationship with TSMC, taping out its next flagship smartphone SoC on TSMC’s N2P process . For MediaTek, the EMIB-T bet is a dual-track strategy to ensure it can serve its AI-chip ambitions without being constrained by a single-supplier bottleneck, even if that means navigating the immense technical risk of bringing a new packaging technology to market.