How Siemens Veloce helps validate Arm’s AGI CPU before tapeout

In other words, Siemens is helping Arm test more of the AGI CPU and its software environment earlier than a first-silicon-only approach would allow.

Why the Arm AGI CPU raises the validation bar

Arm positions the AGI CPU for agentic AI infrastructure and says it delivers more than 2x performance per rack compared with x86 platforms ^[1]. Siemens says the processor is built on the Arm Neoverse Compute Subsystem V3 platform and is designed for high-performance, energy-efficient compute in agentic AI and cloud data-center deployments ^[5].

The design context is complex. Siemens points to a multi-die CSS architecture, Neoverse V-series cores, high-speed interconnects and interfaces such as PCIe Gen6, NVMe and CXL ^[5]. That mix makes validation more than a matter of checking isolated blocks. The difficult questions are system questions: how cores, interconnects, I/O, power behavior and software interact under data-center-style conditions.

What Veloce Strato CS contributes before tapeout

Veloce Strato CS is the emulation layer in the Siemens flow. Siemens describes it as a hardware-assisted verification platform and says it supported Arm AGI CPU verification from subsystem through full-system level ^[5]. That is the level of validation needed to look for integration issues that may not appear when individual blocks are tested alone.

Scale is the key point. Siemens says Arm used multiple Veloce Strato CS towers for full-system verification of the AGI CPU ^[5]. For a large data-center CPU, that scale helps engineers exercise broader system behavior before physical silicon is available, including performance, latency and power-related targets cited by Siemens ^[5].

Siemens also says Arm used its hardware-assisted verification, emulation and prototyping workflows to validate key performance metrics for the Neoverse V-series Compute Subsystem used in the AGI CPU ^[5]. The value before tapeout is straightforward: the earlier a chip team can expose system-level problems, the more room it has to adjust the design and software flow before production silicon.

What Veloce proFPGA CS adds for software readiness

Emulation addresses hardware and system verification, but a data-center CPU also needs firmware, drivers and platform software to be ready. Siemens says Veloce proFPGA CS is being used for FPGA-based pre-silicon software development and can run prototypes at near-real-time speeds so teams can begin validation, driver development and system bring-up before silicon availability ^[5].

That is especially important for cloud infrastructure. A CPU can meet hardware goals and still face delays if the software stack is not ready. FPGA prototyping gives teams a practical target for earlier bring-up work while the real chip is still unavailable.

What the Siemens validation does not prove

The Siemens announcement supports a clear conclusion: Arm is using large-scale, hardware-assisted verification and FPGA prototyping to reduce pre-silicon risk around the AGI CPU ^[5]. It does not independently prove final production-silicon performance.

That distinction matters for Arm’s performance messaging. Arm says the AGI CPU delivers more than 2x performance per rack compared with x86 platforms ^[1]. The cited materials establish that as Arm’s launch claim, not as a third-party benchmark result. The cited materials also do not disclose a final tapeout date or production-silicon validation data.

Bottom line

Siemens is helping Arm move AGI CPU validation earlier in the chip cycle. Veloce Strato CS gives Arm a way to emulate and verify the processor from subsystem to full-system scale, while Veloce proFPGA CS gives software teams a pre-silicon platform for validation, driver development and bring-up ^[5].

The result is a validation flow aimed at finding hardware, performance, power, latency, integration and software-readiness issues before the AGI CPU reaches production silicon. The caveat is equally important: this is evidence of a serious pre-silicon validation strategy, not independent proof of Arm’s final performance claims.