Huawei's Tau Scaling Law: How 3D LogicFolding Bypasses US Sanctions to Target 1.4nm-Class Chips by 2031

From Shrinking Transistors to Shrinking Time

The fundamental idea behind the Tau Scaling Law is to focus on τ (tau), the signal propagation time, as the core metric of progress . By optimizing how quickly a signal moves through devices, circuits, chips, and full systems, Huawei claims it can extract more performance and efficiency from existing manufacturing nodes.

This matters because Moore's Law, which long depended on doubling transistor density every 18 to 24 months through lithography advances, has been slowing down globally due to physical and economic limits . Huawei is positioning Tau as a successor principle that works within the constraints of its sanctioned reality .

LogicFolding: The Sanctions Workaround in Practice

The Tau Scaling Law would remain a purely theoretical exercise without LogicFolding, the practical chip architecture Huawei announced alongside it . Instead of a single plane of logic transistors, LogicFolding stacks multiple layers vertically—essentially building a 3D logic chip.

Huawei reports that a double-layer LogicFolding implementation increases transistor density by 55% and improves power efficiency by 41% . Critically, all of this can be manufactured using older deep ultraviolet (DUV) lithography tools, which are not covered by the most restrictive US sanctions that block access to ASML's EUV machines .

First commercial roadmap: 2026

• The first LogicFolding chips will appear in new Kirin smartphone processors later this year, achieving a claimed density of 238 million transistors per mm² .
• These chips are expected to debut in Huawei's Mate 90 series smartphones .

Long-term target: 1.4nm-equivalent by 2031

• By stacking three layers, Huawei projects that its high-end chips will reach transistor density equivalent to a 1.4-nanometre process by 2031 .
• This would put it near the global frontier of chipmaking, close to where TSMC, Samsung, and Intel are expected to be by the end of the decade .
• The entire roadmap is designed to be achievable solely with DUV lithography .

Strategic Significance for China's Semiconductor Self-Sufficiency

The announcement was immediately read as more than a product roadmap. Analysts described it as a potential "DeepSeek moment" for China's semiconductor sector—an architectural breakthrough that attempts to bypass, rather than simply endure, the US hardware blockade .

Several factors elevate the strategic importance:

• First Chinese global framework: Chinese state media highlighted that this is the first time China has proposed a guiding principle intended for the global semiconductor industry, rather than following roadmaps set by Western companies and consortia .
• Dual-use across smartphones and AI: The Tau Scaling Law and LogicFolding are designed to improve both consumer Kirin smartphone SoCs and Huawei's Ascend AI accelerators, directly targeting the domestic AI chip market where Nvidia currently holds a strong position .
• Self-reliant chip ecosystem milestone: The announcement reinforces Beijing's broader push to build a domestic chip ecosystem that is not dependent on foreign lithography tools, a goal that US sanctions were designed to thwart .

Huawei stated it has already designed and mass-produced 381 chips based on Tau Scaling Law principles .

What Huawei Hasn't Shown Yet

The announcement generated headlines worldwide, but important caveats remain. Huawei did not provide independent performance data or verified benchmarks at the conference .

Equivalent density is not equivalent performance
Transistor density is only one variable in chip performance. Achieving a 1.4nm-equivalent transistor count through 3D stacking does not automatically equal the power characteristics, clock speeds, thermal behavior, or manufacturing yield of a true 1.4nm node fabricated by TSMC or Samsung on an advanced process .

Thermal challenges of vertical stacking
Stacking logic layers introduces significant thermal dissipation complexity. Heat generated in the middle of a 3D stack is harder to remove, and managing this without throttling performance or reducing reliability is a known engineering hurdle for all 3D-integrated designs .

Ambitious timeline, unvalidated yield
Moving from a proven double-layer chip in 2026 to a high-yield triple-layer commercial product by 2031 is an aggressive timeline. Outside analysts have not yet validated whether the claimed density, power, and yield targets can be achieved on schedule .

A Pivot in the US-China Chip War

Whether or not Huawei hits every milestone on time, the Tau Scaling Law and LogicFolding announcement signals an important strategic pivot. Rather than waiting for sanctions to lift or for domestic EUV capability to mature, Huawei is attempting to redefine what counts as semiconductor progress on terms that its available tools can satisfy .

If the approach yields competitive results in real-world products, it could validate a new architectural path that other sanctioned Chinese firms follow—and potentially influence the global industry's response to the end of geometric scaling, even outside China.