Huawei's Tau Scaling Law: The Plan to Build 1.4 nm Chips Without ASML

The companion architecture that makes this practical is called LogicFolding. Rather than pushing for smaller transistors on a single plane using the EUV lithography that remains out of reach, LogicFolding stacks logic circuits vertically in a 3D structure. According to Huawei, the technique boosts transistor density by roughly 55% and improves power efficiency, all while using mature, accessible fabrication nodes . He Tingbo also published a companion mathematical framework, 'A Time Scaling Theory for Multi-Layer Electronic Systems,' on ChinaXiv.org .

Huawei's stated ambition is to reach transistor densities equivalent to a 1.4-nanometer-class process by 2031, without ever possessing ASML's most advanced extreme ultraviolet lithography machines . The first fully Tau Law-designed Kirin chip is expected to appear in a Mate-series device later this year .

Why this matters: sanctions, strategy, and system-level scaling

The significance of the Tau Scaling Law is impossible to separate from the sanctions box that Huawei has been operating in since 2019. Denied access to the world's most advanced fabrication tools, the company's semiconductor roadmap would, on paper, have hit a hard ceiling at relatively mature process nodes. The Tau Law represents an attempt to break through that ceiling by changing the rules of the game entirely .

Huawei claims to have spent the past six years applying the framework in silence, mass-producing 381 different chip designs based on the approach . He Tingbo described the experience to Xinhua with the phrase: 'No way back is the way to victory' .

The strategy repositions the entire competition. Instead of trying to catch up on the traditional Moore's Law curve—which would require unrestricted access to global lithography supply chains—Huawei is attempting to convince the industry that the true metric of progress should be time-to-result at the system level, not transistor count on a spec sheet . It's a play to redefine semiconductor leadership on China's own terms, with a particular focus on AI clusters and data-center performance where system-level latency matters more than individual transistor density .

The caveats

It is important to note that no independent third party has verified Huawei's performance or yield claims. The much-cited 1.4 nm-equivalent transistor density by 2031 is a Huawei projection, not an independently benchmarked result . The commercial viability of vertically stacked logic circuits has troubled the wider industry for years due to heat dissipation and manufacturing complexity. Whether LogicFolding can solve those problems at scale remains an open question.

Still, the Tau Scaling Law marks a genuine milestone: it is the first time a major Chinese technology company has attempted to set a new guiding principle for the global semiconductor industry, rather than simply following one written in the West .