Inside the Kirin 9030 Pro: What the First STEEL Lab Teardown Reveals About China's Most Advanced Chip

Even more striking is the local metal pitch. SMIC N+3 achieved a minimum metal pitch (M0) of 32.5 nm—about 10% tighter than the 36 nm pitch found in Intel's shipping Panther Lake processors built on Intel 18A . SemiAnalysis was careful to note that this is a cherry-picked metric and not representative of overall process parity .

All of this was done without any EUV tools, relying entirely on aggressive deep ultraviolet (DUV) multi-patterning and design-technology co-optimization (DTCO) . The result is a genuine engineering feat, but SemiAnalysis emphasizes the costs: extreme process complexity, lower yields, and significant expense that prevent N+3 from matching TSMC N6 on maturity or cost .

The report consistently describes N+3 as SMIC's third-generation 7nm-class process, not a true 5nm node . An earlier TechInsights teardown from December 2025 confirmed similar conclusions, placing N+3 at approximately 6nm-class density, below the true 5nm nodes from TSMC and Samsung .

Performance: Three Years Behind Current Flagships

SemiAnalysis' benchmark analysis positions the Kirin 9030 Pro as roughly three years behind the current crop of flagship SoCs—though in many cases the gap looks even larger .

CPU

• The Taishan v124 prime core, clocked at 2.75 GHz, has instructions-per-clock (IPC) comparable to Arm's Cortex-X2 from 2021 .
• Apple's 2020 M1 Firestorm core still holds a 35% IPC lead. The latest Apple M5 P-core is 60% higher in IPC and achieves 2.7x higher absolute performance .
• Geekbench 6 scores for the Kirin 9030 Pro sit at approximately 1,131 single-core / 4,277 multi-core, trailing the Snapdragon 8 Elite Gen 5 by over 300% in single-core and 245% in multi-core tests .

GPU

• The in-house Maleoon 935 GPU roughly matches 2022 flagship levels and slightly exceeds the Snapdragon 8+ Gen 1 in 3DMark Wild Life Extreme .
• Against the current Snapdragon 8 Elite Gen 5, the gap widens to 2.4x–2.6x .

Efficiency
The efficiency gap is even wider than raw performance. SemiAnalysis highlighted a stark comparison: Apple's low-power efficiency core delivers 20% higher integer performance while drawing roughly 1W, versus Huawei's prime core at 4.5W . The root cause, SemiAnalysis argues, is not design capability—Huawei's core design is near the level of last-generation industry leaders—but the manufacturing deficit. Apple and Qualcomm are running on TSMC N4 and N3P, giving them fundamental voltage-frequency curve advantages that SMIC cannot match with DUV-only N+3 .

LogicFolding: Huawei's Sanctions Bypass Strategy

SemiAnalysis positions Huawei's LogicFolding initiative as a direct strategic response to being denied EUV lithography—a shift away from traditional transistor shrinks toward 3D stacking as the primary scaling vector . Huawei publicly detailed the architecture at the IEEE ISCAS 2026 conference in Shanghai on May 25, 2026 .

Tau (τ) Scaling Law
Huawei's He Tingbo proposed the Tau Scaling Law as an alternative to Moore's Law. Instead of geometric transistor scaling, the focus shifts to reducing signal transit time through vertical integration and tighter die-to-die interconnects .

LogicFolding Architecture
LogicFolding vertically stacks digital, analog, and memory circuits into active layers, using advanced hybrid bonding to shorten critical paths across dies . Huawei claims this delivers a 55% increase in transistor density and a 41% improvement in energy efficiency on a fixed process node . The company says 381 chips using these principles have already been mass-produced over the past six years .

The roadmap targets 1.4 nm-class mass production by 2031—without EUV . The upcoming Kirin 2026 SoC (arriving fall 2026) is expected to reach approximately 238 MTr/mm², matching Intel 18A density, with a performance core frequency of 3.1 GHz . Subsequent annual iterations are planned at 3.39 GHz (2027), 3.71 GHz (2028), and 3.97 GHz (2029) . SemiAnalysis has also noted that Huawei's hybrid bonding pitch is already at 1.5 µm for the 2026 chip and will shrink to 1 µm next year, giving it a 16–36x denser interconnect than competitors .

Caveats
SemiAnalysis flags that Huawei's own technical paper suggests denser 3D LogicFolding for the Ascend AI accelerator line may slip to around 2030, with near-term Ascend chips staying on 2.5D packaging and chiplets . This creates a split timeline: consumer Kirin SoCs test the LogicFolding architecture first, while high-end AI chips trail by several years . The teardown report cautions that while N+3's individual metrics are impressive, the fundamental process deficit is still large, making LogicFolding a necessary but unproven long-term gamble .