Huawei’s Tau Scaling Law: A New Path Beyond Traditional Chip Scaling

Huawei used the 2026 IEEE International Symposium on Circuits and Systems in Shanghai to present what it calls the Tau (τ) Scaling Law. In a keynote titled “New Semiconductor Path in Practice,” He Tingbo argued that future chip progress should be guided less by the physical shrinking of transistors and more by reducing the time required for signals and workloads to move through electronic systems. 23

The proposal is best understood as a design framework rather than a new manufacturing process. Huawei links it to LogicFolding, software–hardware co-optimization and system interconnect technologies intended to improve performance, energy efficiency and effective transistor density as conventional geometric scaling becomes harder to sustain. 12

What Tau scaling changes

Traditional geometric scaling measures progress largely through smaller transistor dimensions and greater transistor density. Huawei’s proposed τ scaling instead makes signal-propagation delay and overall execution time the central optimization targets. The company says that reducing these delays across the full technology stack could produce gains even when transistor shrinkage slows. 235

That does not mean transistor size becomes irrelevant. Rather, Huawei is presenting a broader way to measure progress: optimize the resistance, capacitance, wiring, architecture and data movement that determine how quickly a system can perform useful work.

How Huawei says the framework works

Huawei describes the approach as coordinated optimization across four levels:

1. Device level: reduce resistance and parasitic capacitance

At the device and interconnect level, the objective is to reduce resistance and parasitic capacitance. These electrical properties contribute to signal delay and energy use, so improving them can shorten the time constants of transistors and the connections between them. 2

2. Circuit level: shorten critical paths

At the circuit level, Huawei points to reducing the length of critical-path wiring and lowering resistive and capacitive loading. The goal is to move signals through logic more quickly and reduce the energy required for each operation. LogicFolding is presented as one of the technologies supporting this layer of the strategy. 25

3. Chip level: coordinate software, architecture and silicon

Huawei’s proposal also moves beyond isolated circuit improvements. At the chip level, it calls for software, architecture and silicon to be designed together around actual workloads. That means optimizing instruction flow, data flow and parallel execution rather than treating raw transistor count as the only meaningful measure of capability. 2

4. System level: make communication part of scaling

At the system level, Huawei connects τ scaling with its UnifiedBus interconnect and “cluster + SuperPoD” architecture. Huawei says UnifiedBus is designed to support large AI training and inference systems by connecting processors with high bandwidth, low latency and unified memory addressing so the infrastructure can behave more like a single logical computer. 17

Those are architectural goals and company claims, not independently established industry standards. The relevance to Tau scaling is that communication between chips and servers becomes part of the performance equation: reducing interconnect delays can improve the effective speed of the entire system, even when individual transistors are not dramatically smaller.

What Huawei reported about deployment

Huawei said it had applied the Tau Scaling Law to smartphone and AI-computing products and had designed and mass-produced 381 chips based on the approach over the previous six years. That figure comes from Huawei’s own disclosure. 2

The company also said that Kirin smartphone chips planned for fall 2026 would be the first to fully adopt its LogicFolding architecture. 257

Huawei’s longer-term target is for high-end chips designed under the framework to reach transistor density equivalent to a 14 Å, or 1.4nm, process by 2031. This is a density-equivalence goal, not evidence that Huawei has already produced an independently verified 1.4nm manufacturing process. 251231

Is Tau Scaling a replacement for Moore’s Law?

Not yet. Huawei is positioning τ scaling as a successor or alternative guiding principle because the historical gains from transistor shrinkage have become more difficult and expensive. But calling it a “law” does not make it a universally accepted physical law, and the available reporting does not independently verify all of Huawei’s projected performance, efficiency or density gains.

The underlying engineering ideas—reducing resistance, capacitance, wiring delay, data movement and system communication overhead—are familiar forms of optimization. Huawei’s distinct claim is that these techniques should be coordinated and used as the industry’s primary scaling framework across devices, circuits, chips and complete computing systems. 1219

Why the announcement matters

The proposal reflects a broader shift in advanced computing: when leading-edge process improvements slow, performance can increasingly depend on architecture, packaging, memory movement, interconnects and workload-specific software. In that sense, Tau scaling is less a claim that geometry no longer matters than an argument that time-to-compute should matter just as much as transistor dimensions.

He Tingbo also called for openness and cooperation among scientists, engineers and industry partners, framing semiconductor progress as a problem that cannot be solved by one company alone. 2

For now, the practical test will be whether upcoming Kirin and AI products can demonstrate measurable gains from LogicFolding and the wider τ-scaling approach. Until those results are independently assessed, Huawei’s announcement should be read as an ambitious semiconductor roadmap—not as proof that Moore’s Law has already been replaced.