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Why Jensen Huang Says Huawei’s Tau Scaling Is a Breakthrough—but Not a Threat to TSMC
On May 28, 2026, Jensen Huang called Huawei’s Tau Scaling a breakthrough for Huawei but not a threat to TSMC. Tau Scaling shifts attention from shrinking transistors to reducing signal propagation time through 3D layouts, chip stacking, and advanced interconnects.
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Key takeaways
- On May 28, 2026, Jensen Huang called Huawei’s Tau Scaling a breakthrough for Huawei but not a threat to TSMC.
- Tau Scaling shifts attention from shrinking transistors to reducing signal propagation time through 3D layouts, chip stacking, and advanced interconnects.
- Huawei’s planned LogicFolding based Kirin chip for autumn 2026 will be an important test, but independent performance and mass production results are not yet available.
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openai.comCreate a landscape editorial hero image for this Studio Global article: What did NVIDIA CEO Jensen Huang say during his May 28, 2026 visit to Taiwan about Huawei’s newly proposed Tau (τ) Scaling Law—particularly. Article summary: Huang’s reported message was essentially: Huawei’s Tau approach is “a breakthrough for Huawei,” but it is “not a threat to TSMC,” because it is an alternative use of 3D integration rather than a new replacement for leadi. Topic tags: general, general web, news, user generated. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks, charts wi
Jensen Huang’s message in Taiwan was measured rather than dismissive: Huawei’s Tau (τ) Scaling Law is a meaningful breakthrough for Huawei, but it does not currently threaten TSMC. His reasoning was that Huawei is applying a promising 3D integration strategy to an industry problem that TSMC and other chipmakers have already been developing for years. 6
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The distinction matters because Huawei’s announcement has sometimes been interpreted as evidence that the company has reached 2nm, 1nm, or 1.4nm manufacturing. The available evidence supports a narrower conclusion: Huawei has proposed a way to improve effective density and signal speed without relying solely on further lithographic shrinking, but the architecture still needs to prove its performance, yield, thermal behavior, and economics at scale. 1
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What Huawei’s Tau Scaling Law is trying to change
Traditional semiconductor scaling largely focuses on making transistors smaller. Huawei’s Tau Scaling Law proposes making signal movement faster by reducing propagation delay across devices, circuits, chips, and systems. The Greek letter τ refers to the time associated with that delay. 2
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LogicFolding is the architectural technique Huawei presented alongside the law. It reorganizes circuits that would traditionally be arranged in a flat, two-dimensional layout into more tightly connected vertical structures. The stated goal is to place logic, analog, and memory functions closer together, shortening critical signal paths and improving effective density without requiring a new transistor-generation process node. 1
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Reports on Huang’s comments describe the approach as using chiplet stacking and hybrid bonding to increase the number of transistors in a chip—potentially doubling, tripling, or even quadrupling counts—without making the semiconductor line width smaller. Those are reported capabilities of the approach, not independently verified results from a shipping product. 6
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Why Huang called it a breakthrough for Huawei
For Huawei, the attraction is strategic as well as technical. An architecture that extracts more performance or density from available manufacturing processes could provide another route forward while access to some advanced chipmaking tools remains restricted. Huawei has said that its high-end chips could reach transistor density equivalent to a 1.4nm process by 2031. 4
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That would be significant if achieved. It would show that system architecture, interconnects, and packaging can supplement transistor scaling when physical shrinking becomes more difficult or less accessible.
But “1.4nm-equivalent” is not the same as manufacturing transistors on a genuine 1.4nm process. Huawei’s target refers to transistor-density equivalence, and available reporting says the company did not provide independent performance data to establish that its future chips would match the overall performance, power efficiency, yield, or reliability of a leading-edge 1.4nm-class process. 1
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Why he said it was not a threat to TSMC
Huang’s comparison was fundamentally about maturity and execution. TSMC has already spent years developing die stacking, 3D integration, and advanced packaging as complements to conventional transistor scaling. In the reports of Huang’s remarks, he said TSMC and Taiwan had possessed related technology for about a decade. 7
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TSMC’s own response made a similar distinction, describing Huawei’s proposal as “3-D scaling, not revolutionary.” The company also emphasized that advanced packaging, chip stacking, and other integration methods are becoming increasingly important alongside continued improvements in transistor density.
That does not make Huawei’s work irrelevant. It means that LogicFolding is not automatically a replacement for TSMC’s process technology or manufacturing ecosystem. TSMC can combine smaller transistors with advanced packaging, while Huawei is presenting vertical integration as a more central alternative to continued geometric shrinking. The competitive question is therefore not whether 3D integration exists, but who can design, manufacture, bond, test, yield, and scale the complete system reliably and economically.
The key technical risks are still ahead
A stacked design can shorten signal paths, but adding vertical layers also creates difficult engineering problems. Heat must be removed from a denser structure, the bonding and post-processing steps must achieve high yields, and designers must verify and test the resulting system. EDA workflows, thermal management, repairability, and mass production can all become more complicated as more functions are integrated vertically. 1
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These challenges are especially important because Huawei’s most visible near-term milestone is still a plan. The company has said that Kirin smartphone chips using a Tau Scaling architecture called LogicFolding are scheduled for autumn 2026, but reports note that the product has not yet supplied independently benchmarked results or established a confirmed high-volume production record. 3
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What to watch next
The first meaningful test will be whether a LogicFolding-based Kirin chip delivers measurable advantages in real products rather than only in architectural projections. Useful evidence would include independent benchmarks, power measurements, sustained thermal performance, manufacturing yield, and proof that Huawei can produce the design at commercially relevant volume.
The longer-term test is Huawei’s 2031 density target. Even if the company reaches 1.4nm-equivalent transistor density, that result should be evaluated separately from the name of the process node. Chip performance depends on more than transistor count: interconnect delay, memory access, power delivery, cooling, software, packaging quality, and production consistency all matter.
The bottom line
Huang’s reported position can be summarized in one sentence: Huawei’s Tau Scaling Law may be a major domestic breakthrough because it offers a credible alternative path to better chip density and signal speed, but it is not yet a near-term displacement threat to TSMC’s leading-edge manufacturing and packaging capabilities. 6
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The fairest reading is not that Huawei has already achieved 2nm, 1nm, or 1.4nm manufacturing. It is that Huawei has proposed a 3D architectural strategy that could extract more usable performance from less advanced manufacturing—and now has to prove that strategy with independent results and reliable mass production. 1
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What is the short answer to "Why Jensen Huang Says Huawei’s Tau Scaling Is a Breakthrough—but Not a Threat to TSMC"?
On May 28, 2026, Jensen Huang called Huawei’s Tau Scaling a breakthrough for Huawei but not a threat to TSMC.
What are the key points to validate first?
On May 28, 2026, Jensen Huang called Huawei’s Tau Scaling a breakthrough for Huawei but not a threat to TSMC. Tau Scaling shifts attention from shrinking transistors to reducing signal propagation time through 3D layouts, chip stacking, and advanced interconnects.
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Huawei’s planned LogicFolding based Kirin chip for autumn 2026 will be an important test, but independent performance and mass production results are not yet available.