Huawei’s Tau Scaling Law Explained: LogicFolding, 1.4nm Density and the TSMC Gap

Huawei has proposed a way to keep advancing chip performance even when access to the most advanced manufacturing equipment is restricted. At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, He Tingbo, Huawei’s semiconductor-business president and chair of its Scientist Committee, presented the company’s Tau (τ) Scaling Law and its LogicFolding architecture. 1

The headline target is ambitious: Huawei says high-end chips could reach transistor density equivalent to a 1.4nm—or 14A—process by 2031. But the wording matters. Huawei is describing 1.4nm-equivalent density achieved through design and system-level optimization, not announcing that it can already fabricate a literal 1.4nm process independently of TSMC or other leading foundries. 14

What Huawei announced at IEEE ISCAS 2026

He Tingbo’s keynote, titled “New Semiconductor Path in Practice,” presented Tau Scaling as a new principle for semiconductor and electronic-system development. Instead of treating ever-smaller physical features as the primary measure of progress, Huawei says engineers should focus on reducing the time constant—particularly the time required for signals to move through a computing system. 16

Huawei describes this as replacing, or at least moving beyond, conventional geometric scaling with time (τ) scaling. The idea is not to abandon process technology. Rather, it is to coordinate improvements at multiple layers so that chips can deliver more useful computation with less delay and energy, even when transistor dimensions cannot keep shrinking at the same pace.

How LogicFolding is supposed to work

LogicFolding is the central architecture Huawei associated with the new scaling principle. The company says it can reorganize logic beyond traditional planar layouts, shortening critical signal paths and reducing the resistance and capacitance associated with interconnects. That could improve effective transistor density while also helping performance and energy efficiency. 14

The broader approach is described as a stack of coordinated optimizations:

• Device level: reduce resistance, parasitic capacitance and other contributors to the time constant.
• Circuit level: use LogicFolding to shorten important paths and pack logic more efficiently.
• Chip level: coordinate software, architecture and hardware around real workloads.
• System level: reduce communication and memory-access delays across connected components. 1

This is why the announcement should be understood as a design methodology rather than a new lithography process. A smaller process node can provide denser transistors, but architecture, interconnects, packaging and workload-specific design can also affect how much useful performance a complete system delivers.

What the 381-chip claim means

Huawei says the Tau Scaling framework has already supported the design and mass production of 381 chips over the past six years, spanning smartphone and artificial-intelligence computing applications. 16

That figure is presented by Huawei as evidence that the approach has been tested in production rather than remaining only a theoretical proposal. However, the supplied reporting does not provide an independent audit of all 381 chips or a standardized comparison of their performance, density and power efficiency. The number should therefore be treated as a Huawei company claim, not as independently verified proof of a new industry-wide scaling law.

Huawei also said a new Kirin smartphone processor planned for fall 2026 will fully adopt LogicFolding. 4 The commercial chip will be an important test: independent teardowns and benchmarks should help establish whether the architecture produces the claimed gains in real products.

Why the 1.4nm target is easy to misunderstand

A process-node label such as “1.4nm” is often used as shorthand for a generation of manufacturing technology, but Huawei’s stated goal is narrower and more specific. The company is targeting transistor density equivalent to a 1.4nm-class process through architecture and system design. 18

That does not mean a Huawei or Chinese foundry has demonstrated a 1.4nm production line. The distinction separates three different claims:

1. A true 1.4nm manufacturing node: the fabrication process itself produces features associated with that technology generation.
2. 1.4nm-equivalent transistor density: a chip contains a comparable number of transistors per area through design, layout or integration techniques.
3. Comparable system performance: the finished product delivers similar results in a particular workload.

Those outcomes can overlap, but they are not interchangeable. Huawei’s announcement supports the second claim as a stated objective. It does not, by itself, establish the first or guarantee the third.

The TSMC and export-control context

The strategy is significant because Huawei lost access to the leading external chip-manufacturing pipeline after U.S. restrictions affected companies using U.S. technology to produce chips for HiSilicon. Huawei has since had to rebuild more of its semiconductor supply chain around domestic capabilities, including SMIC.

U.S. export controls also restrict China’s access to advanced semiconductor technologies and manufacturing equipment. A 2025 report citing TechInsights said SMIC was still struggling to transition to next-generation production, with a Huawei laptop using a chip based on the older 7nm N+2 process. That gap helps explain why Huawei is emphasizing improvements that can be made in chip architecture and system design rather than relying entirely on access to the newest lithography tools.

The company has already demonstrated that domestic production can support a partial recovery. Huawei’s 2023 Mate 60 Pro used a domestically produced 7nm-class processor made by SMIC, marking its return to a 5G-capable flagship smartphone after restrictions had severely damaged its consumer-electronics business.

What the announcement proves—and what it does not

Huawei’s presentation establishes that the company is pursuing a coordinated, design-led route to chip scaling and has attached concrete milestones to it. The most immediate milestone is the planned fall 2026 Kirin chip; the longer-term ambition is 1.4nm-equivalent density by 2031. 14

It does not prove that Huawei has matched TSMC’s most advanced manufacturing technology, that SMIC can currently produce a genuine 1.4nm node, or that LogicFolding will deliver the projected gains in consumer and AI products. Those questions depend on manufacturing yield, power consumption, software compatibility, benchmark results and independent technical analysis.

The strategic implication is still substantial. If Huawei can extract more performance and density from constrained process technology, it may reduce the practical impact of its manufacturing disadvantage. The company’s proposal is therefore best read as an attempt to change the measure of progress: from asking only how small a transistor is to asking how efficiently an entire computing system moves and processes information.

For now, Tau Scaling and LogicFolding are promising but largely company-reported claims. The 2026 Kirin launch and subsequent independent testing will determine whether Huawei has found a durable alternative path—or mainly a new way to describe optimization within existing manufacturing limits.