What the September device would prove: It will be an important commercial test, not proof by announcement. Industry analysts will need to establish the chip’s actual process technology and yield; measure CPU/GPU/NPU performance, power and thermals; inspect its packaging and memory system; and compare sustained real-world performance—not just peak benchmarks—with leading chips. A favorable result would show that architecture and integration can narrow a gap despite weaker leading-edge manufacturing; it would not show that Huawei has replaced EUV lithography or repealed the economics of transistor scaling.

Two models of the AI stack: Huang’s five-layer cake is a deliberately high-level industrial map: energy → chips → computing infrastructure → cloud/AI models → applications. Liao’s 18-story pagoda unpacks those categories into dependencies from theory, power and natural resources through materials, silicon, transistor/process design, fabrication, lithography, packaging, architecture, runtimes and quantization, then training, models, agents and applications. The point is to expose the components hidden inside “chips,” “infrastructure,” and “models.”

Why the “shortest layer” matters: Liao’s bottleneck argument is essentially end-to-end systems engineering. The most capable model cannot compensate for inadequate power, memory bandwidth, packaging, fabrication yield, software tooling, interconnects, or deployment capability; throughput, cost and reliability are constrained by the weakest dependency. The pagoda is therefore an argument for strengthening interfaces and coordination across the whole stack, rather than treating a fast accelerator as sufficient.

Clusters as compensation: The strategic implication is to seek useful system-level performance from many domestically available, individually less capable accelerators: co-design chips, memory, networking, compiler/runtime, model quantization and distributed-training software so the cluster spends less time communicating or sitting idle. This can be effective for workloads that parallelize well, but it can entail greater power, networking, software-complexity and operational costs than using fewer frontier GPUs. The available reporting supports this as Huawei’s strategy; independent validation of parity with leading Nvidia systems is still insufficient.

China ecosystem and market context: The approach fits a broader push for an integrated domestic stack—chip design and fabrication, memory, packaging, AI frameworks and system integration—because an import restriction at any one layer can cap the entire system. IDC data reported by Reuters show domestic Chinese GPU/AI-chip suppliers, led by Huawei, held about 41% of China’s AI-accelerator server market in 2025, while Nvidia remained the leader at 55%; export controls and localization pressure are major drivers of that shift.

What the September device would prove: It will be an important commercial test, not proof by announcement. Industry analysts will need to establish the chip’s actual process technology and yield; measure CPU/GPU/NPU performance, power and thermals; inspect its packaging and memory system; and compare sustained real-world performance—not just peak benchmarks—with leading chips. A favorable result would show that architecture and integration can narrow a gap despite weaker leading-edge manufacturing; it would not show that Huawei has replaced EUV lithography or repealed the economics of transistor scaling.

Two models of the AI stack: Huang’s five-layer cake is a deliberately high-level industrial map: energy → chips → computing infrastructure → cloud/AI models → applications. Liao’s 18-story pagoda unpacks those categories into dependencies from theory, power and natural resources through materials, silicon, transistor/process design, fabrication, lithography, packaging, architecture, runtimes and quantization, then training, models, agents and applications. The point is to expose the components hidden inside “chips,” “infrastructure,” and “models.”

Why the “shortest layer” matters: Liao’s bottleneck argument is essentially end-to-end systems engineering. The most capable model cannot compensate for inadequate power, memory bandwidth, packaging, fabrication yield, software tooling, interconnects, or deployment capability; throughput, cost and reliability are constrained by the weakest dependency. The pagoda is therefore an argument for strengthening interfaces and coordination across the whole stack, rather than treating a fast accelerator as sufficient.

Clusters as compensation: The strategic implication is to seek useful system-level performance from many domestically available, individually less capable accelerators: co-design chips, memory, networking, compiler/runtime, model quantization and distributed-training software so the cluster spends less time communicating or sitting idle. This can be effective for workloads that parallelize well, but it can entail greater power, networking, software-complexity and operational costs than using fewer frontier GPUs. The available reporting supports this as Huawei’s strategy; independent validation of parity with leading Nvidia systems is still insufficient.

China ecosystem and market context: The approach fits a broader push for an integrated domestic stack—chip design and fabrication, memory, packaging, AI frameworks and system integration—because an import restriction at any one layer can cap the entire system. IDC data reported by Reuters show domestic Chinese GPU/AI-chip suppliers, led by Huawei, held about 41% of China’s AI-accelerator server market in 2025, while Nvidia remained the leader at 55%; export controls and localization pressure are major drivers of that shift.