Inside Huawei’s Plan to Build 1.4nm-Class Chips Without ASML’s EUV Machines

The strategy centers on breaking free from the industry’s dependence on ASML’s extreme ultraviolet (EUV) lithography machines, which China has been blocked from buying. Instead of racing to shrink transistors—the traditional Moore’s Law path now gated by EUV tool access—Huawei’s new framework tries to change the game. The announcement, made by semiconductor chief He Tingbo at the IEEE International Symposium on Circuits and Systems in Shanghai on May 25, 2026, laid out a roadmap to achieve transistor density equivalent to a 1.4-nanometer process node by 2031, all while still using older deep ultraviolet (DUV) lithography tools .

What Is the Tau Scaling Law?

The Tau (τ) Scaling Law is Huawei’s proposed replacement for Moore’s Law. Rather than measuring progress by how small a transistor can be etched, it measures it by signal propagation delay—the time it takes for data to travel through a chip and across a system . The goal is to compress this time constant, tau, across four levels simultaneously: the device level (minimizing resistance and parasitic capacitance), the circuit level, the chip level, and the full system level .

This is a wholesale shift in optimization targets. Where the industry has historically chased smaller geometries, Huawei is now chasing a faster signal. The company’s official announcement describes the law as “a new guiding principle for the evolution of both semiconductors and electronic systems” .

What Is the LogicFolding Architecture?

LogicFolding is the physical implementation of the Tau Scaling Law. It is a vertical 3D logic stacking technique that folds logic circuits into multiple layers, shortening the critical-path wiring and reducing the resistive and capacitive load that slows signals down . Huawei claims this approach can deliver a 55% increase in transistor density over conventional planar designs and a 41% improvement in performance-core energy efficiency .

The roadmap published by Huawei envisions a two-layer chip entering the market in 2026, likely in a new Kirin processor for the Mate 90 series, and a three-layer chip by 2031 capable of reaching transistor density equivalent to what TSMC and Samsung would achieve with a 1.4nm node . Crucially, all of this is planned without EUV lithography .

The Catch: Unproven at Scale

Despite the bold claims, there are several major reasons for skepticism. First, the 55% density gain is a figure provided by Huawei that has not been independently verified . Whether the lab results translate to mass production is an open question. Independent analysis from Reuters described the approach as offering “a path for China to build cutting-edge chips despite U.S. sanctions,” while cautioning that whether it represents a true breakthrough “remains to be seen” .

Second, LogicFolding faces significant practical challenges. Heat dissipation becomes exponentially harder when logic circuits are stacked vertically. The design tool ecosystem needed to reliably implement the architecture is not yet mature, and the manufacturing yield for three-layer logic chips is unproven at commercial scale .

Nvidia CEO Jensen Huang, while calling Huawei’s work “a breakthrough,” said it is “not a threat for TSMC,” noting that TSMC has been using advanced 3D packaging for years and that the real challenge is ramping production . The first real test arrives with the Kirin chip launch later in 2026, which will show whether the claimed density gains survive when millions of units need to be manufactured .

Implications for Samsung and SK Hynix

The implications for South Korean chipmakers vary by their business focus. For Samsung, which competes directly with TSMC in the leading-edge foundry market, Huawei’s strategy poses a conditional threat. If LogicFolding succeeds, it could narrow the manufacturing advantage that Samsung’s EUV-equipped fabs currently enjoy, allowing Huawei to produce competitive AI and server-class logic chips through domestic or China-accessible foundries . That would reduce the premium on EUV access and put price pressure on the foundry business.

For SK Hynix, the threat is more indirect. LogicFolding is a logic-chip architecture; it does not directly address DRAM or high-bandwidth memory (HBM) production. SK Hynix’s core memory business is not the primary target. However, if Huawei succeeds in building a competitive AI chip ecosystem, Chinese firms could rely less on non-Chinese chip suppliers, which could eventually soften demand for the advanced memory products that SK Hynix sells into those systems .

What This Reveals About China’s Broader Semiconductor Strategy

The Tau Scaling Law and LogicFolding reveal a strategy that has evolved well beyond simply trying to catch up on conventional process nodes. China is now attempting to redefine what chip scaling means. Instead of fighting the EUV battle on the terms set by ASML, TSMC, and Samsung, Huawei is trying to change the battlefield itself—measuring progress in time, not in nanometers .

This architectural leapfrogging is part of a broader self-reliance push that spans device, circuit, chip, and system-level optimization, not just lithography . It is also a signal that Washington’s export-control regime, while imposing real costs, has not halted Chinese chip progress. Instead, it has channeled enormous resources into alternative paths. Publicly crediting U.S. sanctions as the catalyst for LogicFolding is an attempt to claim that the pressure has backfired .

The unveiling at a major IEEE conference in Shanghai sent a deliberate message that Huawei intends to remain part of the leading-edge semiconductor conversation, restricted tools or not . For policymakers in Washington and competitors in Seoul and Hsinchu, the pressing question is no longer whether China will find ways around the sanctions, but how quickly those workarounds might become competitive.