Huawei’s Tau Scaling Law and LogicFolding: A New Path to 1.4‑nm‑Equivalent Chips

Huawei has introduced a new semiconductor design concept called the Tau (τ) Scaling Law, paired with a chip architecture known as LogicFolding. The company says this approach could eventually enable chips with transistor density equivalent to a 1.4‑nanometre manufacturing node by 2031, even though China currently lacks access to the most advanced fabrication tools used by leading chipmakers.

The proposal represents a shift away from the traditional model of progress in semiconductors—shrinking transistor size—and toward architectural and system‑level optimization.

Why Huawei Is Looking Beyond Traditional Scaling

For decades, the semiconductor industry followed Moore’s Law, improving performance primarily by shrinking transistors to fit more of them onto each chip. But two major pressures are making that approach harder for Huawei:

• Physical and economic limits on continued transistor miniaturization.
• Export controls that restrict Chinese companies’ access to cutting‑edge semiconductor manufacturing equipment, including extreme ultraviolet (EUV) lithography tools.

China’s top foundry partner for Huawei, SMIC, is still producing advanced chips around the 7‑nm level, several generations behind leading global manufacturers.

Because manufacturing progress is constrained, Huawei is emphasizing design‑driven improvements that extract more capability from existing fabrication technology.

The Tau (τ) Scaling Law Explained

Huawei unveiled the Tau Scaling Law at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) as a new principle to guide semiconductor development.

Instead of focusing only on physical transistor shrinkage, the law proposes replacing geometric scaling with “time scaling.”

In simple terms:

• Geometric scaling (traditional): Improve chips by making transistors physically smaller.
• Time scaling (Tau scaling): Improve chips by reducing the time signals need to move through circuits and systems.

The idea is to continuously reduce the system’s time constant (τ)—the delay associated with signal propagation and computation—across multiple layers of design.

If signal delays shrink and circuit organization becomes more efficient, the system can behave as though it has higher transistor density and better performance even without shrinking every transistor.

Some coverage has referred to the idea as “Her’s Law,” describing it as a conceptual shift from Moore’s geometry‑based progress to time‑based optimization of computing systems.

LogicFolding: The Architecture Behind the Concept

To implement the Tau Scaling approach, Huawei introduced a core technology called LogicFolding.

This architecture reorganizes how circuits are arranged so that signals travel shorter distances and encounter less electrical resistance and capacitance.

Reported goals include:

• Reducing signal propagation delay
• Lowering resistive and capacitive load in circuits
• Increasing effective transistor density
• Improving performance and energy efficiency

Some descriptions suggest the technique can reorganize circuits into stacked or folded structures, shortening signal paths and allowing denser layouts without requiring a smaller manufacturing node.

Huawei says these optimizations can be coordinated across multiple layers—from device and circuit design to chip and system architecture—to improve overall performance.

Already Used in Hundreds of Chips

Huawei says the design philosophy behind Tau scaling has already been used in hundreds of chip designs developed over the past several years.

The company also plans to introduce LogicFolding in upcoming Kirin processors, beginning with new smartphone chips expected to appear in future Huawei devices.

If successful, these chips would serve as the first real‑world test of the architecture in high‑volume consumer products.

The Strategic Importance for China

The announcement has significance beyond chip design. It reflects China’s broader push to develop a self‑reliant semiconductor ecosystem.

U.S.‑led export controls have limited China’s access to advanced semiconductor equipment and technologies, especially EUV lithography systems used for cutting‑edge manufacturing nodes.

Without those tools, catching up to companies like TSMC or Samsung through conventional scaling alone is difficult. Huawei’s proposal attempts to reduce dependence on those manufacturing advances by emphasizing architectural innovation instead.

What Remains Unproven

Despite the ambitious claims, the Tau Scaling Law remains largely a roadmap rather than a verified breakthrough.

Reports note that Huawei has not released independent benchmark results or third‑party validation showing that the approach can truly match the transistor density or performance of future 1.4‑nm chips.

Whether the concept can deliver gains comparable to leading‑edge fabrication nodes will likely depend on real‑world results from upcoming chip generations.

The Bigger Picture

If Huawei’s approach works even partially, it would illustrate a broader industry trend: future chip improvements may rely increasingly on architecture, packaging, and system design—not just smaller transistors.

For Huawei and China’s semiconductor sector, the Tau Scaling Law represents an attempt to keep advancing computing capability despite limits on access to the world’s most advanced manufacturing technologies.