US vs China AI Chips: Architecture, Performance, and Ecosystem Compared

Architecture and Compute Performance

US accelerators currently lead in documented raw compute throughput for large‑scale AI training. For example, AMD’s MI325X reaches roughly 1.3 PFLOPS FP16 performance, while Google’s TPU v6e delivers 918 TFLOPs bf16 per chip.

Chinese chips such as Huawei’s Ascend 910C aim to narrow this gap, with estimates of around 800 TFLOPS FP16 using a dual‑chiplet configuration derived from earlier Ascend chips.

Biren’s BR100 accelerator represents another Chinese attempt to compete at the high end, delivering up to 256 TFLOPS FP32 compute and around 2,048 TOPS INT8 performance in a multi‑die GPU design.

Cambricon’s MLU370‑X8 targets AI inference and training workloads with 256 TOPS INT8 and 96 TFLOPS FP16 compute capability.

Memory and Bandwidth

Modern AI models rely heavily on memory capacity and bandwidth, making HBM integration critical.

• The AMD MI325X includes 256GB of HBM3E memory and about 6 TB/s bandwidth, one of the largest memory capacities among AI accelerators.
• TPU v6e uses 32GB HBM with roughly 1.6 TB/s bandwidth, but is designed to scale to hundreds of interconnected chips in TPU pods.
• Huawei Ascend 910C reportedly reaches about 3.2 TB/s memory bandwidth, supporting large‑scale model workloads.
• Biren BR100 includes 64GB HBM2E memory and around 2.3 TB/s bandwidth.

Higher memory bandwidth helps accelerate matrix operations and large‑model training, which often move massive tensors across memory and compute units.

Interconnect and Scaling

Large AI models are rarely trained on a single chip. Instead, hundreds or thousands of accelerators are connected into clusters.

• Google’s TPU v6e chips connect using a dedicated Inter‑Chip Interconnect (ICI) network designed for TPU pods containing up to 256 chips.
• Cambricon’s MLU370‑X8 uses MLU‑Link, providing 200GB/s communication throughput between cards for multi‑GPU training.
• Biren GPUs include high‑speed GPU‑to‑GPU interconnect links designed for multi‑accelerator clusters.

Cluster architecture is increasingly as important as the individual chip’s raw compute performance.

Manufacturing and Supply Chains

Manufacturing technology strongly influences performance and energy efficiency.

Many Chinese AI chips rely on external fabrication technologies. For example, Biren’s BR100 was built using TSMC’s 7‑nm process and advanced CoWoS packaging.

Huawei’s newer Ascend chips combine designs produced on SMIC’s 7‑nm‑class process with earlier wafers produced before US export restrictions.

In contrast, US‑designed chips typically rely on advanced foundries and supply chains capable of producing cutting‑edge nodes and packaging technologies.

Ecosystem and Software

Hardware performance alone does not determine success in AI computing.

• US chips benefit from mature ecosystems such as CUDA (Nvidia), ROCm (AMD), and Google’s TPU software stack.
• Huawei promotes the CANN (Compute Architecture for Neural Networks) framework for Ascend chips to build a domestic AI software ecosystem.

Developer tooling, frameworks, and cloud integration often determine which hardware is adopted for real‑world AI workloads.

What the Comparison Shows

Several patterns emerge from the current generation of AI accelerators:

• Performance leadership: US accelerators currently show higher documented peak compute and memory capacities.
• Domestic alternatives: China has built multiple competing chip lines—including Ascend, Biren GPUs, and Cambricon accelerators—to reduce dependence on US hardware.
• Cluster strategy: Both sides increasingly compete through large AI systems and supercomputer‑scale clusters rather than individual chips.

The AI chip race is therefore not just a contest of transistor counts or TFLOPs—it is also a competition between ecosystems, manufacturing capability, and the ability to scale thousands of accelerators into efficient AI infrastructure.

As generative AI models continue to grow, these differences in architecture, memory systems, and software ecosystems will likely determine which platforms dominate future AI computing.