Inside Google's Multi-Foundry 'Icefish' Strategy to End TSMC Dependency

The Icefish Manufacturing Split: TSMC and Samsung

The proposed division of labor for the Icefish chip is a clear case of strategic decoupling. Google is not simply dual-sourcing an identical chip; it is breaking the processor into its constituent parts and assigning them to different foundries based on their capabilities .

• TSMC: The Computing Engine. The most performance-critical portion of the Icefish TPU—the main compute die—will remain with TSMC . Sources suggest this core component will be manufactured on one of TSMC's most advanced nodes, likely a 2nm-class or even a 1.4nm process technology, though Google has not confirmed the exact node .
• Samsung: The Memory I/O Die. Samsung Foundry is being considered to manufacture a secondary but essential memory input-output (I/O) die, the component that manages the high-speed data pathway between the compute die and memory . Production would use Samsung’s 2nm (SF2) process, a cutting-edge node that the company was the first to initiate mass production on in mid-2025 .

This split allows Google to continue leveraging TSMC's world-leading performance for the core logic while opening up a new capacity pipeline with Samsung for a component that is vital but slightly less demanding. However, no formal agreement has been signed, and the talks remain preliminary. Google executives visited Samsung's advanced fab in Taylor, Texas in December 2025 to discuss production viability and volumes .

Decoding MediaTek's Role: It's Not for Icefish

Amid the flurry of reports, confusion has emerged over the role of Taiwanese chip designer MediaTek. A careful reading of the sources clarifies that MediaTek’s involvement is not directly on the Icefish v10 chip itself. Instead, its engineering contribution is firmly positioned on an earlier generation of Google’s TPU roadmap .

MediaTek is actively participating in the design of Google's 8th-generation TPU series, which includes the TPU 8t (“Sunfish,” a training chip) and TPU 8i (“Zebrafish,” an inference chip). These chips are targeting TSMC's 2nm node and are slated for late 2027 . For this project, MediaTek's role is to provide I/O modules and back-end manufacturing coordination, leveraging its immense supply-chain scale and lower pricing to help Google optimize costs, while Google retains full architectural control over the core computing design .

For the Icefish (v10) project, Google’s primary design implementation partner remains Broadcom, its long-standing collaborator for high-performance TPU cores since at least the TPU v2 .

The Strategic Imperative: Escaping the TSMC Bottleneck

The multi-foundry Icefish plan is a direct response to two converging and urgent pressures that threaten Google’s ability to scale its AI infrastructure.

1. TSMC's Capacity is the Binding Constraint. TSMC is the world’s sole mass-producer of the most advanced AI chips, and its capacity—specifically its Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging—is dangerously tight. CoWoS is required to integrate the logic dies with high-bandwidth memory (HBM) into a single module for top-tier AI accelerators, and Nvidia, as TSMC’s largest customer, consumes a dominant share of this capacity .

Estimates for Google’s 2026 TPU shipments range from 3.3 to 4.6 million units, not constrained by demand but by the physical allocation of CoWoS capacity . Some industry analysis suggests Google has been forced to cut its production targets as it loses packaging capacity to larger rivals .

2. Geopolitical Concentration Risk. Relying on a single Taiwanese foundry for all advanced AI chip production represents a profound geopolitical vulnerability that Google, like many global tech giants, is now actively mitigating .

The dual-source strategy for Icefish is just one front in a comprehensive, multi-pronged diversification campaign that now includes:

• Intel Foundry: A reported firm order for over 3 million custom TPUs for 2028 production, potentially representing roughly half of Google’s projected 6-million-unit volume across the 2027-2028 period . Unlike the Samsung agreement for an I/O die, some reports suggest Intel’s deal may cover the manufacture of complete TPU systems .
• A Multi-Partner Design Ecosystem: Google has assembled at least four chip design partners—Broadcom for high-performance training cores, MediaTek for optimizing inference chips, Marvell for networking and custom memory processing units, and Intel—creating pricing competition and eliminating single-source design risk .
• Deepening In-House Expertise: Google continues to hire aggressively for TPU co-design roles, reinforcing its retention of architectural control across all generations of its custom silicon, a critical move to avoid vendor lock-in .

Important Caveats

All plans described above are based on reports from The Information, Reuters, and other outlets citing anonymous sources familiar with the discussions. Neither Google, Samsung, TSMC, Intel, nor MediaTek have issued official confirmation . The Icefish project remains in active development, and the discussions with Samsung are preliminary, with no definitive agreement in place . Furthermore, there is some inconsistency across reports on whether Intel's reported 3-million-unit order is specifically for Icefish chips or other TPU generations like Ironwood; the most cautious reading is that Intel will handle a substantial portion of Google’s total TPU volume across 2027 and 2028 .