Huawei’s Top Scientist Warns Nvidia Is Heading for a Physical ‘Avalanche’ — and Pitches a Different Path

Liao stated that the economic benefit of Moore's Law — the reduction of cost per transistor — effectively ended at the 16nm and 7nm nodes. Today, only performance and energy-efficiency gains remain, but those too are diminishing . He specifically warned that Nvidia's strategy of building massive monolithic dies packed with HBM to drive AI performance will be the first to suffer from these physical constraints. "Expanding scale by continuously adding more transistors and higher bandwidth memory is becoming unsustainable," he said .

The Alternative: Tau Scaling Law and LogicFolding

Huawei's proposed alternative was formally unveiled in May 2026 at the IEEE International Symposium on Circuits and Systems in Shanghai, and expanded on by Liao in the July interview .

Tau Scaling Law: This is Huawei's proposed replacement for Moore's Law. Instead of measuring progress by transistor size (nanometers), the Tau Scaling Law optimizes for τ (tau) — signal transit time across the entire computing stack. The goal is to minimize data movement latency rather than shrink feature sizes .

LogicFolding architecture: This is the hardware implementation of the Tau Law. LogicFolding is a 3D-like chip design technique that stacks logic circuits vertically within the same die . Huawei claims LogicFolding can achieve a 53.5% higher transistor density while staying on existing, accessible lithography nodes (i.e., without requiring extreme ultraviolet (EUV) lithography machines that Huawei cannot access due to U.S. sanctions) . Huawei has publicly targeted producing "1.4nm-class" chips by 2031 using this design methodology, effectively claiming it can bypass EUV restrictions through architectural innovation rather than process shrinks .

Strategic and Geopolitical Context

These claims cannot be separated from Huawei's position in the U.S.-China tech war. The Tau Scaling Law and LogicFolding are explicitly framed as a path to build cutting-edge chips without access to advanced Western lithography tools (ASML EUV scanners) or leading-edge foundries like TSMC, both of which are denied to Huawei under U.S. export controls .

Liao acknowledged that Huawei cannot beat Nvidia in a single-card, brute-force specs war. Instead, he argued that the future belongs to system-level performance — using Huawei's full-stack software (CANN, MindSpore) and large-scale cluster networking to make up for individual chip shortcomings .

The interview was a rare public appearance by a top Huawei chip architect. Framing the West's current advantage as a "dead end" and Huawei's constrained path as "the future" serves both as a technical argument and as a morale-boosting narrative for China's domestic semiconductor ecosystem .

External Skepticism

Reuters and other outlets noted that while the approach is novel, it remains unproven at scale. Whether LogicFolding can deliver real-world performance parity with Nvidia's next-generation architectures is an open question, and some analysts view it as a workaround rather than a true breakthrough . The first real-world test will be Huawei's next smartphone chip, which Liao said will be dissected later in 2026 to show how far the approach narrows the gap with rivals .