Samsung V10 BV-NAND Explained: 400+ Layers and a New Bonded-Wafer Architecture

Samsung’s V10 Bonding V-NAND, or BV-NAND, is a 10th-generation 3D NAND design built around wafer bonding and a stack of more than 400 word lines. Samsung positions it as a storage technology for AI-era systems that need higher capacity, faster data movement and lower power consumption. 12

The company’s August 31 disclosures put the headline gains over V9 at more than 58% higher bit density, I/O speeds above 4.8 Gbps—over 33% faster—and more than 25% lower power consumption. 28

How V10 reaches more than 400 layers

Rather than manufacturing the entire ultra-tall cell structure as one stack, Samsung says V10 uses a three-stack HARC Merge process. The cell layers are divided into three stack sections, manufactured separately and connected vertically. Multi Hole and Zero Dummy Hole techniques are also used to manage the process challenges associated with very high layer counts. 1317

This approach is significant because increasing NAND density is not simply a matter of adding more layers. As stacks become taller, manufacturing, alignment and electrical-performance challenges become harder to manage. Splitting the structure into multiple sections gives Samsung a way to extend the vertical architecture while addressing those process constraints. The supplied sources establish the three-stack structure and supporting techniques, but do not provide a complete process-level description of every manufacturing step.

What the bonded-wafer design does

V10 separates the NAND cell array from its peripheral, or “Peri,” circuitry. Samsung fabricates those elements on separate wafers and then bonds the wafers together. This lets the cell array and its control circuitry be developed and optimized independently before they are combined. 2512

The design is intended to improve density and performance without relying solely on making a single wafer stack taller. Samsung also says the bonded architecture helps support higher-performance peripheral circuitry, which contributes to the improvements in data transfer and power efficiency reported for V10. 213

The “full capping” footprint question

The supplied reporting describes “full capping” as a layout in which the lower peripheral die is matched to the footprint of the upper cell-array die, rather than extending beyond it. That would help preserve package and chip-area efficiency while retaining the advantages of separately fabricated cell and peripheral wafers.

However, the provided primary Samsung material and source excerpts clearly support the separate-wafer and bonding architecture, but do not independently document the finer geometric details of the “full capping” terminology or verify the exact footprint-matching implementation. That distinction matters: the broad architecture is disclosed, while the precise layout interpretation should be treated cautiously.

V10’s claimed improvement over V9

Samsung’s disclosed comparison with its ninth-generation V-NAND is:

• Bit density: more than 58% higher.
• I/O speed: more than 4.8 Gbps, representing an improvement of more than 33%.
• Power consumption: more than 25% lower. 2817

Higher bit density can enable more storage capacity within a comparable physical area. Samsung has linked V10 to future high-capacity SSD designs, including solutions supporting capacities of up to 128 TB and next-generation PCIe Gen7 SSDs, according to reporting on the company’s plans. 13

Those figures are Samsung’s stated performance claims, not independent benchmark results. The available material does not establish how the gains will translate across particular SSD products, workloads or controller configurations.

Why Samsung is targeting AI storage

AI data centers require large amounts of storage for training data, model checkpoints and other data-intensive workloads. NAND is not a substitute for the bandwidth characteristics of high-bandwidth DRAM, but it can serve the capacity-oriented storage layer where density and energy use are important.

Samsung presented V10 as part of a broader AI-memory strategy that also includes zHBM and zNAND-O. The company describes zHBM as a concept for placing high-bandwidth memory closer to—or vertically above—an AI accelerator, while zNAND-O is a high-performance NAND concept being developed in four- and eight-layer versions. 567

The common theme is vertical integration: use three-dimensional packaging or memory structures to address space, bandwidth, power and thermal constraints. V10 is the storage-focused part of that portfolio, while zHBM and zNAND-O remain concept or development architectures in the supplied evidence rather than shipping products with confirmed production schedules. 167

Commercialization and longer-term roadmap

Samsung introduced V10 as a prototype and next-generation technology at the 2026 Future of Memory and Storage conference. The August 31 interview and the supplied reporting do not provide a firm mass-production or shipment date. 12

That means several roadmap claims should not be presented as confirmed commitments. The supplied evidence does not substantiate a definitive V10 commercialization schedule, an 11th-generation NAND launch in 2027 or a 1,000-layer NAND target by 2030. Earlier reports have discussed a 1,000-layer goal, but those reports are not equivalent to a confirmed timetable from Samsung. 2526

For now, the clearest conclusion is narrower: V10 demonstrates Samsung’s move beyond 400 NAND layers using a three-stack cell architecture and bonded cell/peripheral wafers, with company-claimed gains in density, I/O and power efficiency. Its commercial availability and the pace of future generations remain open questions.