Inside Intel's EMIB-T Breakthrough: Solving Underfill, Power, and Cooling for 15–25 kW AI Packages

Intel's Rio Rancho, New Mexico facility is at the center of a major leap in advanced semiconductor packaging. The company has detailed a suite of technologies designed to shatter the physical limits of chip packaging, enabling ultra-large, multi-kilowatt AI accelerators that would be impossible with today's standard methods. The heart of this push is EMIB-T, a next-generation interconnect technology that addresses power delivery, mechanical reliability, and thermal management for the largest package designs ever conceived.

The Core Breakthrough: EMIB-T with Through-Silicon Vias

Intel's central innovation is EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Vias), disclosed in detail at the Electronic Components Technology Conference (ECTC) 2026. EMIB-T adds vertical through-silicon vias (TSVs) to existing EMIB silicon bridges, enabling both higher-density lateral interconnects and vertical power delivery through the bridge itself . Intel has validated EMIB-T at a 36/35 µm bump pitch on a 2× reticle-sized package — a 65% increase in bump density over the 45 µm pitch used in Granite Rapids . The technology is slated for production fab rollout in 2026 .

Solving Underfill Encapsulation for Packages Up to 24× Reticle

One of the biggest challenges for ultra-large packages is mechanical stress and voiding during underfill encapsulation. Intel uses distributed mold underfill (DMU) technology to address this. By distributing the underfill material across multiple dispensing zones, DMU prevents cracking, delamination, and void formation on packages that far exceed the single-reticle size limit . This is critical because Intel's packaging roadmap targets packages greater than 12× reticle size by 2028, and the company has demonstrated conceptual capability up to 24× reticle for future AI super-chip designs .

Validated Package Configurations and Roadmap

Intel has published a clear roadmap from current production to future targets :

• Current production: 8× reticle size packages shipping from Rio Rancho, New Mexico.
• Validated at ECTC 2026: 2× reticle package with EMIB-T at 36/35 µm pitch .
• Production rollout 2026: EMIB-T entering fab production this year .
• 2028 roadmap: >12× reticle size (single package >10,000 mm²) .
• Future target: Up to 24× reticle for extreme-scale AI chips .

Intel also demonstrated a 10-2-10 thick-core glass substrate at NEPCON Japan 2026, aiming for world-first mass production of glass substrates for AI chip packaging at Rio Rancho .

Power, Cooling, and Energy Storage for 15–25 kW Packages

Hyper-large packages present unprecedented challenges in power delivery, heat extraction, and transient power smoothing. Intel is developing a multi-pronged infrastructure strategy to support packages operating at 15–25 kilowatts :

• Power delivery via EMIB-T TSVs: The through-silicon vias in EMIB-T enable much higher current delivery directly through the bridge interconnects, supporting HBM4/4e-class memory power requirements .
• Distributed heat extraction: Intel has demonstrated a new distributed heat dissipation architecture for ultra-large packages, moving beyond traditional single-point thermal solutions .
• Microfluidic cooling: At ECTC 2026, Intel presented microfluidic cooling advances integrated directly into the package substrate to handle the extreme thermal density of multi-kilowatt chips .
• On-package energy storage: Intel has disclosed capacitor-integrated substrate technologies to smooth transient power delivery for 15–25 kW package domains .

These technologies are designed to work in concert, allowing a single package to draw and dissipate power levels previously reserved for entire server racks.

External Partners: Expanding the Ecosystem

Intel is building a broad ecosystem to bring EMIB-T and glass substrate packaging to the broader market.

Tessolve (EMIB-Based Design Enablement)

On July 27–28, 2026, Tessolve announced a collaboration with Intel Foundry to support package designs using EMIB technology . Tessolve is now positioned to help Intel Foundry customers with heterogeneous multi-chiplet EMIB designs, providing end-to-end semiconductor design and packaging services. This enables a broader ecosystem of chip designers to adopt Intel's advanced packaging without building in-house expertise.

Lens Technology (Glass Substrate Packaging)

On July 24, 2026, Intel signed a memorandum of understanding with Lens Technology, a Chinese precision glass manufacturer, to jointly explore through-glass via (TGV) advanced packaging for glass substrates . Lens Technology is constructing a dedicated 30,000 m² glass substrate facility for this effort . The collaboration is currently non-binding and focused on process development and validation, not yet a committed production contract .

EDA Vendors

Intel also has all three major EDA vendors (Cadence, Synopsys, Siemens EDA) in its Chiplet Alliance Program developing EMIB-T design workflows .

Competitive Landscape: How Intel Stacks Up Against TSMC, Samsung, and AMD

Intel's packaging push is a direct challenge to the established leaders in advanced packaging.

• TSMC remains the volume leader. Its CoWoS (Chip-on-Wafer-on-Substrate) platform is the primary packaging solution for NVIDIA and AMD AI accelerators. TSMC demonstrated direct-to-silicon liquid cooling on CoWoS at ECTC 2025, achieving 0.055°C/W thermal resistance at 2.6 kW+ TDP on 3,300 mm² interposers . TSMC has also announced glass core substrate development but targets the "second half of this decade" for production — trailing Intel's 2026 glass substrate push . CNBC reported in April 2026 that NVIDIA was snapping up CoWoS capacity and exploring Intel as a secondary packaging supplier, indicating TSMC is supply-constrained .

• Samsung offers I-Cube (2.5D) and X-Cube (3D) packaging. Samsung is aggressive on hybrid copper bonding (HCB) for 3D stacking and has its own glass substrate program, but has disclosed less detail on reticle-scale packages beyond 4–6×.

• AMD relies primarily on TSMC CoWoS for its MI300/MI400 series AI accelerators and uses its own Infinity Architecture for chiplet interconnect. AMD does not operate its own packaging fabs, so it is a customer — not a direct packaging technology competitor.

Key Comparison: Intel vs. TSMC

Metric	Intel (Rio Rancho)	TSMC (CoWoS)
Max package size (today)	8× reticle (~7,000 mm²)	~3.3× reticle (~3,300 mm² interposer)
Roadmap	>12× by 2028, up to 24×	Scaling incrementally
Bump pitch validated	36/35 µm (EMIB-T)	~40–45 µm on CoWoS-L
Production thermal capability	15–25 kW target (multi-chip)	2.6 kW+ demonstrated
Glass substrates	10-2-10 thick-core demo'd, mass production target 2026–2027	Production target "2nd half of decade"

Intel's differentiation is package size leadership and vertical integration (design + fab + packaging under one roof). TSMC's edge is proven high-volume manufacturing maturity, a vast customer ecosystem, and superior thermal performance per mm² today. Intel's bet is that the AI industry will need packages far larger than what CoWoS can efficiently serve, and that its Rio Rancho facility can deliver those before competitors scale up.