The tool was used to auto-generate verification code and build virtual test environments, tasks that previously required engineers to manually study communication protocols and construct behavioral models from scratch .
Samsung's broader Device Solutions (DS) division disclosed earlier in March 2026 that AI had already shortened some analog and logic chip module design cycles by 50% . These results are part of a wider trend: Samsung also reported that AI compressed process design kit (PDK) adaptation iteration time by over 95% in its memory chip division, with those tools now deployed in mass-production R&D .
Important caveat: These are task-specific gains, not a blanket productivity multiplier across all chip design. Verification-oriented behavioral modeling and test infrastructure show the clearest improvements, while more complex or creative design tasks may not benefit equally .
Samsung's AI adoption addresses two structural workforce constraints:
The productivity gains come with several documented risks, observed both at Samsung and across the broader industry:
The reported gains are real but narrowly scoped: 15x on one SoC verification workflow and 50% on some module designs — not a universal productivity improvement across all semiconductor R&D tasks. The primary workforce challenge addressed is a structural talent shortage, and AI is acting as a force multiplier for existing teams. The key risks — LLM hallucinations, unauthorized RTL modification, error masking, and data-security history — mean that Samsung's AI rollout remains cautious, with all outputs requiring 100% human review and enterprise-grade security controls in place.
The tool was used to auto-generate verification code and build virtual test environments, tasks that previously required engineers to manually study communication protocols and construct behavioral models from scratch .
Samsung's broader Device Solutions (DS) division disclosed earlier in March 2026 that AI had already shortened some analog and logic chip module design cycles by 50% . These results are part of a wider trend: Samsung also reported that AI compressed process design kit (PDK) adaptation iteration time by over 95% in its memory chip division, with those tools now deployed in mass-production R&D .
Important caveat: These are task-specific gains, not a blanket productivity multiplier across all chip design. Verification-oriented behavioral modeling and test infrastructure show the clearest improvements, while more complex or creative design tasks may not benefit equally .
Samsung's AI adoption addresses two structural workforce constraints:
The productivity gains come with several documented risks, observed both at Samsung and across the broader industry:
The reported gains are real but narrowly scoped: 15x on one SoC verification workflow and 50% on some module designs — not a universal productivity improvement across all semiconductor R&D tasks. The primary workforce challenge addressed is a structural talent shortage, and AI is acting as a force multiplier for existing teams. The key risks — LLM hallucinations, unauthorized RTL modification, error masking, and data-security history — mean that Samsung's AI rollout remains cautious, with all outputs requiring 100% human review and enterprise-grade security controls in place.