How PSMC and UMC Became Intel's Key Partners in the EMIB-T Challenge to TSMC's CoWoS

For years, TSMC's CoWoS (Chip-on-Wafer-on-Substrate) has been the undisputed standard for packaging the world's most advanced AI accelerators—Nvidia's H100, AMD's MI300, and every generation of Google's TPU. But a structural capacity crunch, with CoWoS-L sold out through 2026 and lead times stretching to 78 weeks, has created the biggest opening in years for an alternative . Intel's EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Vias) is the most credible challenger, and it is building a real supply chain to back that ambition—anchored by two Taiwanese partners: Powerchip (PSMC) and United Microelectronics Corporation (UMC) .

PSMC's Exclusive Role: The Silicon Capacitor Supplier with Fully Booked Capacity

PSMC has secured the role of exclusive supplier of silicon capacitors for Intel's EMIB-T advanced packaging through its 12-inch integrated passive device (IPD) platform . After achieving EMIB certification and entering stable production in July 2026, PSMC is reportedly ramping to 10,000 12-inch wafers per month by 2027, with its capacity already fully booked .

This is not a small ancillary role. Silicon capacitors are critical for power delivery in these massive AI packages, and PSMC's exclusive designation signals that Intel has committed to a single, validated source for this key component—at least for the initial production ramp.

UMC's Downstream Role: Building the Silicon Bridges

UMC is also seeing a significant order boost as it manufactures integrated passive devices (IPDs) that are sourced by PSMC for supply to Intel's EMIB-T chain . According to reports, UMC manufactures the EMIB silicon bridges at its 12-inch fabs in Taiwan and Singapore .

This makes UMC a secondary but important node in the same supply pipeline—PSMC acts as the certified supplier and UMC as a foundry partner feeding into that channel. Together, they create a Taiwan-centric supply hub for Intel's EMIB-T, mirroring TSMC's own CoWoS supply concentration around local partners .

EMIB-T vs. CoWoS: The Core Architectural Difference

The fundamental innovation of EMIB is architectural: instead of placing all chiplets on a large, expensive silicon interposer (CoWoS's approach), EMIB embeds small silicon bridges directly into the organic substrate, placed only where chip-to-chip links are needed . EMIB-T adds through-silicon vias (TSVs) to the bridge, enabling vertical power delivery—critical for HBM4-class AI accelerators .

Here is how the two platforms compare on key metrics:

Dimension	Intel EMIB-T	TSMC CoWoS
Cost	~40–50% cheaper than CoWoS	Higher (large interposer approach)
Bridge/package yield	~90% (bridge)	98%+ targeting for CoWoS platforms
Substrate yield	~50% (key bottleneck)	Higher maturity
Mass production target	2027–early 2028	Already in volume production
Capacity constraint	Growing; substrate-limited	CoWoS-L sold out through 2026 into 2027
Reticle scaling (2027)	8–10× reticle size	5.5–9.5× reticle (CoWoS-L)

TSMC's CoWoS capacity is projected to grow from ~675k wafers/month in 2025 to 1.275M in 2026 and 2.31M in 2027 . Yet demand is so intense that the platform remains structurally sold out for premium AI customers, creating a massive tailwind for Intel's EMIB-T .

The Google TPU Win: Intel Foundry's Defining Moment

Google's next-generation TPU, codenamed "Humufish" (v9), is set to use Intel EMIB-T instead of TSMC CoWoS, according to SemiAnalysis and multiple corroborating reports . This marks the first flagship AI chip from a top hyperscaler to publicly break from CoWoS.

Alphabet has placed a foundry order for over 3 million TPU chips with Intel, scheduled for delivery before 2028—the largest AI chip volume contract Intel Foundry has ever secured . Google is expected to produce more than 6 million TPUs between 2027 and 2028, with Intel's foundry portion accounting for approximately half of the total output in 2028 .

Google's own TPU roadmap shows the v8 generation (Sunfish/Zebrafish) remaining on TSMC N2/CoWoS for 2027 H2, while v9 Humufish shifts to Intel EMIB-T specifically to relieve CoWoS bottlenecks . The decision is driven by both cost and capacity: Google moves to Intel's packaging for a ~50% cost advantage while also building a relationship with a second high-volume packaging supplier .

The Critical Risk: Substrate Yield Bottleneck

This is the one number that keeps the EMIB-T narrative from being a clean victory. While Intel's EMIB-T bridge yields reportedly exceed 90% at the validation level, substrate yields remain near 50% . This is the bottleneck that prevents full-scale mass production.

Intel CEO Lip-Bu Tan confirmed at the J.P. Morgan Global Technology Conference that customers are prepaying Taiwanese and Japanese substrate suppliers to secure capacity—with four suppliers from Taiwan and two from Japan requesting upfront commitments . Unimicron, Intel's substrate partner, has stated that EMIB-T will not reach full mass production until early 2028 .

Analyst Ming-Chi Kuo noted that TSMC's 5.5-reticle CoWoS platforms target yields starting around 98% in 2026, giving Intel a significant yield gap to close .

Strategic Implications for 2027–2028

Industry reconfiguration is underway. CoWoS capacity constraints are forcing hyperscalers to qualify alternative packaging, and Intel's EMIB-T is the most credible alternative available. The platform offers a ~50% cost advantage, validated 36/35 µm bump pitch (65% increase in bump density over Granite Rapids), and 4.5+ reticle package capability .

If Intel resolves the substrate yield issue by 2027–2028, EMIB-T could capture significant AI packaging share from CoWoS, particularly from hyperscalers (Google, potentially Meta) actively seeking a second source to mitigate CoWoS supply risk . If not, the window narrows as TSMC's seismic CoWoS capacity expansion (doubling by 2027) catches up with demand .

The Google win validates Intel Foundry as a viable advanced packaging second-source for the world's largest AI chip buyers. This could catalyze additional design wins from other AI chip designers currently constrained by CoWoS lead times and single-supplier risk .

PSMC's exclusive supplier role and UMC's downstream involvement create a Taiwan-centric supply hub for Intel's EMIB-T—a double-edged sword. It mirrors the geographic concentration risk of TSMC's CoWoS supply chain, but also locks in committed capacity from partners already proven in high-volume foundry operations .