2D Transistors Hit the Factory Floor: ASML, TSMC, and Imec Achieve 50nm Integration on 300mm Wafers

For years, the semiconductor industry has viewed two-dimensional materials—substances just a few atoms thick—as a promising path to extend logic transistor scaling beyond the physical limits of silicon. The problem has always been manufacturing. Getting these delicate materials to work on standard 300mm wafers, at dimensions competitive with cutting-edge silicon, seemed like a distant goal.

That distance just closed significantly. In June 2026, at the IEEE/JSAP Symposium on VLSI Technology and Circuits, a consortium of imec, ASML, and TSMC presented a first-of-its-kind demonstration: scaled n-type and p-type field-effect transistors using 2D channel materials, fully integrated on 300mm wafers with a contacted poly pitch (CPP) of just 50nm .

This is not just another lab experiment. It is the first time complementary 2D transistors—both nFETs and pFETs—have been fabricated together on a full-size production wafer at a pitch widely considered the gateway from academic curiosity to industrial manufacturing .

What exactly did they build?

The team demonstrated two complementary device types, using different atomically thin channel materials :

• nFETs built with MoS₂ (molybdenum disulfide) as the channel.
• pFETs built with either WS₂ (tungsten disulfide) or WSe₂ (tungsten diselenide).

All devices were fabricated on the same 300mm silicon wafer using a scalable integration flow compatible with back-end processing . The choice of tungsten-based pFET materials is especially notable, as imec had previously reported record-breaking pFET performance using monolayer WSe₂ at IEDM 2025, achieving drive currents as high as 690µA/µm .

The key number: 50nm contacted poly pitch

The headline metric is the 50nm CPP achieved for both nFET and pFET devices . In chip manufacturing, contacted poly pitch is one of the most critical measures of transistor density and a direct indicator of how aggressively you can scale a logic process.

To put this in perspective: the industry’s leading-edge silicon nodes today operate at pitches below 50nm. Demonstrating 2D-material transistors at 50nm CPP on 300mm wafers proves these exotic materials can play in the same league, not just in tiny research samples but on the same wafer format used in high-volume fabs .

Three milestones in one integration flow

The joint work achieved three specific, measurable results that mark a clear advance beyond prior 2D material research :

1. World-first scaled nFET and pFET devices at 50nm CPP on 300mm wafers.
2. Both transistor polarities showed extremely low off-state current (Ioff) at zero gate voltage (Vg=0V).
3. The pFET performance using WSe₂ channels approached the levels of record-setting lab-scale devices, validating the integration approach preserves material quality.

Additionally, the CMOS-like integration method yielded up to 94% operational transistors (defined as Imax/Imin greater than 10⁵) across the wafer, confirming the process is both robust and stable .

The process that made it possible

What enabled this jump from lab to fab? The consortium developed a novel integration approach specifically designed for transition metal dichalcogenides (TMDs), the class of 2D materials used for the transistor channels . The flow includes several key process modules critical for industrial viability :

• EUV (extreme ultraviolet) lithography to pattern the tiny features needed for 50nm pitch.
• TMDC material transfer techniques suitable for full wafers.
• High-k dielectric integration for gate stacks.
• Channel isolation and advanced chemical-mechanical planarization (CMP) steps.

This combination of standard semiconductor process tools with tailored 2D-material handling is what makes the result a genuine manufacturing breakthrough, not just a materials science demonstration.

Two barriers broken at once

For 2D transistors to ever replace silicon in logic chips, the industry had to overcome two fundamental challenges . First, someone needed to build a complete integration flow that works on 300mm wafers—the standard for modern chip production. Second, that flow had to work for both n-type and p-type devices at the same tight dimensions, since CMOS logic requires complementary pairs.

The ASML-TSMC-imec work clears both obstacles in a single demonstration. By combining imec’s long-running research into TMD-based devices with ASML’s lithography capabilities and TSMC’s manufacturing expertise, the group showed that 2D material transistors can be fabricated, at scale, with the pitch needed for future logic nodes .

Where this fits in the post-silicon roadmap

This is not a one-off experiment. It is the culmination of a longer arc of sustained progress across the industry.

Imec began working on 300mm integration of 2D FET materials as early as 2018, when it first demonstrated direct MOCVD growth of WS₂ on full-size wafers . In 2019, the research center showed ultrascaled MoS₂ transistors with channel lengths down to 30nm . By 2020, imec formally introduced 2D materials into its logic scaling roadmap, projecting their introduction from the A7 node onward .

More recently, Intel Foundry and imec separately demonstrated 300mm fab-compatible integration of critical 2DFET modules including source/drain contacts and gate stacks at IEDM 2025 . At the same conference, imec’s collaboration with TSMC produced record pFET performance on WSe₂ channels, laying the material foundations for the 2026 breakthrough .

The ASML-TSMC-imec result published in June 2026 pulls these threads together into a single, complete demonstration of complementary 2D transistors at a fab-relevant pitch on production wafers. The integration scheme is expected to be applicable not only to the TMD materials used in this work—MoS₂, WS₂, and WSe₂—but to other 2D channel materials as well .

What comes next

The breakthrough was disclosed as paper T1.3 at the VLSI 2026 symposium, titled “First EUV–enabled Integration Route for 50nm Pitch N and PMOS Transistors with 2D Materials Channel from a 300mm Fab” . While the device characteristics are promising, this remains a research demonstration, not a commercial product. Performance and reliability still need to be proven at tighter pitches, and the industry has yet to standardize on the exact 2D material stack for future nodes.

But the significance is clear: for the first time, the semiconductor industry has tangible proof that 2D transistors can follow the same manufacturing path as silicon. The race to post-silicon logic just got real.