Quantum Machines and NVIDIA Demonstrate End-to-End CUDA-Q Control With NVQLink

Quantum Machines and NVIDIA used IEEE Quantum Week in Toronto to show an end-to-end CUDA-Q application operating across live qubits, Quantum Machines control hardware, GPUs, and CPUs through NVIDIA NVQLink. The reported milestone is less about one isolated quantum operation than about treating a quantum processor and its classical control stack as parts of one schedulable heterogeneous system. 1015

What was demonstrated

According to the companies’ reported demonstration, a single CUDA-Q program ran across live qubits and Quantum Machines’ Pulse Processing Unit while using NVQLink to connect the quantum-control environment with NVIDIA accelerated computing. Quantum Machines characterized it as the first time a quantum-control company had run this kind of end-to-end CUDA-Q program across those resources. 1015

That claim should be read carefully: it is a company and trade-reporting milestone, not an independently established industry benchmark. The reported full measurement-and-control exchange of approximately one microsecond similarly needs independent validation. 1015

How the workflow divides work among qubits, GPUs, and CPUs

The practical idea is resource-aware execution inside one hybrid program:

• Live qubits and the quantum controller handle quantum operations and real-time control.
• GPUs handle latency-sensitive, compute-heavy classical tasks, such as decoding measurement data for quantum error correction.
• CPUs handle general host-side and orchestration work.

NVQLink is designed as the real-time, deterministic-latency interface between a quantum-system controller and high-performance classical resources. That connection is meant to make online workloads—including quantum error-correction processing—part of the operating loop rather than a separate, manually stitched-together pipeline. 115

Why the programming model matters

For developers working in Python, C++, or Quantum Machines’ QUA language, the promise is a higher-level way to describe a hybrid workload. Rather than hand-coding and coordinating low-level pulse-control sequences, processor handoffs, data transfers, and feedback paths, developers can express work in a single CUDA-Q-centered flow that dispatches tasks to the appropriate quantum or classical resource. 15

This does not eliminate the underlying hardware complexity. It shifts more of that coordination into the control, compilation, and orchestration stack—an important distinction for teams trying to build repeatable applications rather than bespoke lab integrations.

Why microsecond-scale feedback is relevant to error correction

Quantum error correction depends on a tight loop: measure error syndromes, decode the measurements classically, and apply or schedule corrective action quickly enough for the quantum state to remain useful. NVIDIA’s NVQLink architecture is explicitly aimed at coupling quantum control with HPC resources for online quantum error correction and other compute-intensive real-time workloads. 1

Quantum Machines and NVIDIA report that their demonstration exchanged measurement data and control decisions in roughly a microsecond. That latency target is meaningful because CPU- and GPU-based decoding or optimization must fit within the time budget imposed by the quantum hardware and control system. 101315

The larger goal: quantum processors as supercomputing resources

The demonstration supports a broader architectural argument: future quantum processors may operate less like isolated instruments and more like specialized accelerators inside quantum-classical supercomputers.

Quantum Machines describes a hierarchy in which quantum controllers support fast feedback, bounded-latency CPU-GPU servers handle tasks such as calibration, optimization, and error-correction decoding, and larger HPC systems schedule broader application workloads. 6 NVIDIA’s IEEE Quantum Week program likewise framed fault-tolerant quantum computing as a full-system challenge spanning the QPU, software stack, accelerated computing, and real-time operation. 2

In that model, the key question is not whether every task runs on a quantum processor. It is whether each task runs on the resource that can complete it within the required latency.

Control-layer work beyond the demo

Quantum Machines paired the integration demonstration with a wider focus on calibration workflows and fault-tolerant system design. IEEE Quantum Week’s official program listed a Quantum Machines keynote, “From Pulse to Platform: Control Layer for FTQC,” alongside NVIDIA’s session on designing an accelerated quantum supercomputer for the fault-tolerant era. 11

That emphasis reflects an important reality: improving qubits alone is not enough for fault-tolerant systems. The surrounding control layer, classical accelerators, orchestration software, and feedback pathways must also scale together.

For now, the Toronto demonstration is best understood as an integration proof point. It shows how a CUDA-Q-based workflow could connect live quantum hardware with CPUs and GPUs through NVQLink; it does not by itself prove a production-ready, fault-tolerant quantum computer. 1015