Remaining Supply Constraints: Memory and ABF Substrates

Jun He explicitly flagged that the bottleneck is moving up the supply chain away from TSMC's own CoWoS capacity:

• HBM memory: HBM supply is functionally sold out through 2026 across all three major DRAM vendors (SK hynix, Samsung, Micron) . There is additional yield risk on HBM4E 12-stack, with industry chatter that some customers may fall back to 8-stack configurations, reducing effective memory per package by roughly 33% .
• ABF (Ajinomoto Build-up Film) substrates: ABF substrates remain the critical bottleneck for high-layer-count flip-chip packages. TSMC's CoWoS capacity itself is fully allocated through 2026 and well into 2027, with lead times of 52–78 weeks for AI packaging orders . The insufficiency of ABF substrate supply is a major structural constraint limiting how many packages TSMC can ship regardless of CoWoS line availability .

Scaling Plans: From 5.5x to 14x Reticle by 2028–2029

TSMC laid out an aggressive reticle-size roadmap on a roughly "one generation per year" cadence:

The 14x reticle CoWoS is expected to integrate approximately 10 large compute dies and 20 HBM memory stacks in a single package, essentially turning the package into a system-level compute substrate . Some sources cite 2028 for the 14x reticle, while others (including Jun He's presentation) reference 2029 for commercial production. The discrepancy likely reflects a 2028 tape-out / 2029 volume ramp .

Key Technical Challenges for Scaling

Scaling to 14x reticle (and beyond) introduces several physical and process hurdles:

• Warpage/mechanical stress: Larger package area creates significant bowing and stress across the interposer, substrate, and die stack, requiring advanced materials and process control .
• Signal integrity and interconnect density: Maintaining high-bandwidth, low-latency connections across a 3× larger footprint demands advances in micro-bumps, silicon vias (TSVs), and redistribution layers .
• Power delivery and thermal management: A 14x package housing ~10 large compute dies plus 20 HBM stacks will draw extremely high power, requiring novel cooling solutions and power-distribution networks .
• Lithography stitching: Packages larger than a single reticle shot require precise multi-shot stitching, a key manufacturing challenge for yield at scale .
• Substrate availability: Larger packages require larger, higher-layer-count ABF substrates — the very component already in shortest supply .

TSMC believes wafer-level CoWoS (rather than panel-level packaging) remains the best path for these largest interconnects, as panel-level technologies cannot yet match CoWoS's interconnect density .

Competitive Positioning vs. Intel

TSMC's OCP APAC disclosures directly contrast with Intel's packaging efforts:

• Yield gap: Multiple industry sources report that Intel's competing EMIB-T (Embedded Multi-Die Interconnect Bridge) advanced packaging technology is still chasing 90% yield, while TSMC's CoWoS has already surpassed 98% in HVM . This is an 8+ percentage-point yield gap at scale.
• Reticle-size roadmap: TSMC targets 14x reticle (~12,000 mm²) by 2028–2029. Intel has publicly promised a 12x reticle package on a similar timeline, placing TSMC roughly 15–20% larger in target area .
• Capacity and ecosystem: TSMC expanded CoWoS capacity by 106% in 2025 and has raised 2026 CapEx to a record $60–64 billion partly to fund further packaging expansion . CoWoS capacity is sold out through 2027, meaning TSMC's customers (Nvidia, AMD, Broadcom, etc.) are locked into TSMC's packaging ecosystem — a structural moat .
• Intel's position: Intel's foundry packaging business (including EMIB-T) is still in the yield-ramp phase and has not yet achieved comparable production scale. The yield and capacity gap means TSMC remains the dominant advanced-packaging supplier for high-end AI accelerators for the foreseeable future.

Bottom Line

TSMC's 5.5x reticle CoWoS has achieved 98–99% HVM yields, shifting the AI chip supply bottleneck away from TSMC's own packaging lines and toward HBM memory and ABF substrate supply. The company plans to scale to 14x reticle (~12,000 mm²) by 2028–2029, capable of integrating ~10 compute dies and 20 HBM stacks — but faces significant mechanical, thermal, and substrate challenges. Relative to Intel's EMIB-T (estimated at ~90% yield), TSMC holds a commanding yield, scale, and capacity lead in advanced packaging for AI.

Remaining Supply Constraints: Memory and ABF Substrates

Jun He explicitly flagged that the bottleneck is moving up the supply chain away from TSMC's own CoWoS capacity:

• HBM memory: HBM supply is functionally sold out through 2026 across all three major DRAM vendors (SK hynix, Samsung, Micron) . There is additional yield risk on HBM4E 12-stack, with industry chatter that some customers may fall back to 8-stack configurations, reducing effective memory per package by roughly 33% .
• ABF (Ajinomoto Build-up Film) substrates: ABF substrates remain the critical bottleneck for high-layer-count flip-chip packages. TSMC's CoWoS capacity itself is fully allocated through 2026 and well into 2027, with lead times of 52–78 weeks for AI packaging orders . The insufficiency of ABF substrate supply is a major structural constraint limiting how many packages TSMC can ship regardless of CoWoS line availability .

Scaling Plans: From 5.5x to 14x Reticle by 2028–2029

TSMC laid out an aggressive reticle-size roadmap on a roughly "one generation per year" cadence:

The 14x reticle CoWoS is expected to integrate approximately 10 large compute dies and 20 HBM memory stacks in a single package, essentially turning the package into a system-level compute substrate . Some sources cite 2028 for the 14x reticle, while others (including Jun He's presentation) reference 2029 for commercial production. The discrepancy likely reflects a 2028 tape-out / 2029 volume ramp .

Key Technical Challenges for Scaling

Scaling to 14x reticle (and beyond) introduces several physical and process hurdles:

• Warpage/mechanical stress: Larger package area creates significant bowing and stress across the interposer, substrate, and die stack, requiring advanced materials and process control .
• Signal integrity and interconnect density: Maintaining high-bandwidth, low-latency connections across a 3× larger footprint demands advances in micro-bumps, silicon vias (TSVs), and redistribution layers .
• Power delivery and thermal management: A 14x package housing ~10 large compute dies plus 20 HBM stacks will draw extremely high power, requiring novel cooling solutions and power-distribution networks .
• Lithography stitching: Packages larger than a single reticle shot require precise multi-shot stitching, a key manufacturing challenge for yield at scale .
• Substrate availability: Larger packages require larger, higher-layer-count ABF substrates — the very component already in shortest supply .

TSMC believes wafer-level CoWoS (rather than panel-level packaging) remains the best path for these largest interconnects, as panel-level technologies cannot yet match CoWoS's interconnect density .

Competitive Positioning vs. Intel

TSMC's OCP APAC disclosures directly contrast with Intel's packaging efforts:

• Yield gap: Multiple industry sources report that Intel's competing EMIB-T (Embedded Multi-Die Interconnect Bridge) advanced packaging technology is still chasing 90% yield, while TSMC's CoWoS has already surpassed 98% in HVM . This is an 8+ percentage-point yield gap at scale.
• Reticle-size roadmap: TSMC targets 14x reticle (~12,000 mm²) by 2028–2029. Intel has publicly promised a 12x reticle package on a similar timeline, placing TSMC roughly 15–20% larger in target area .
• Capacity and ecosystem: TSMC expanded CoWoS capacity by 106% in 2025 and has raised 2026 CapEx to a record $60–64 billion partly to fund further packaging expansion . CoWoS capacity is sold out through 2027, meaning TSMC's customers (Nvidia, AMD, Broadcom, etc.) are locked into TSMC's packaging ecosystem — a structural moat .
• Intel's position: Intel's foundry packaging business (including EMIB-T) is still in the yield-ramp phase and has not yet achieved comparable production scale. The yield and capacity gap means TSMC remains the dominant advanced-packaging supplier for high-end AI accelerators for the foreseeable future.

Bottom Line

TSMC's 5.5x reticle CoWoS has achieved 98–99% HVM yields, shifting the AI chip supply bottleneck away from TSMC's own packaging lines and toward HBM memory and ABF substrate supply. The company plans to scale to 14x reticle (~12,000 mm²) by 2028–2029, capable of integrating ~10 compute dies and 20 HBM stacks — but faces significant mechanical, thermal, and substrate challenges. Relative to Intel's EMIB-T (estimated at ~90% yield), TSMC holds a commanding yield, scale, and capacity lead in advanced packaging for AI.