The central idea fueling this funding is not another GPU challenger. XCENA is positioning its debut product, the MX1, as a fundamentally different category: a computational memory device that integrates processing power directly into the memory layer itself.

The Core Problem: When Data Movement Becomes the Bottleneck

In a conventional server architecture, when data needs to be processed, it makes a costly round trip from DRAM to the CPU or GPU and back again. For AI workloads — think large-scale inference, real-time analytics, and vector database queries — this constant data movement introduces latency, consumes power, and creates a well-known memory wall .

XCENA's founding insight is that many of these data-intensive operations don't actually require a GPU's specialized parallel processing. Routine filtering, searching, and analytical tasks can be handled by simpler, more power-efficient cores placed right next to the memory chips, avoiding the round trip entirely. This approach, called near-data processing (NDP), aims to offload the CPU rather than replace it .

Inside the MX1: A Server's New Secret Weapon, Not a GPU Rival

The MX1 is described as the world's first computational memory product to support both PCIe 6.0 and the CXL 3.2 standard . CXL, or Compute Express Link, provides a high-speed, low-latency pathway between processors and memory, making it the ideal backbone for a device designed to live in the memory tier .

Architecture and Key Specs

Rather than a monolithic accelerator, the MX1 is an appliance packed with thousands of custom RISC-V cores. XCENA's own documentation states these are "1,000s of 1.4GHz RISC-V cores" integrated directly into the memory subsystem . These cores can execute database-like operations (through XCENA's XFLARE software libraries) in place, processing data without moving it to the host CPU .

XCENA's technical approach uses a separate SSD-backed expansion path over PCIe 6.0, enabling what the company calls "Infinite Memory." This feature can theoretically expand a host's accessible memory pool to petabyte-scale using CXL-attached SSDs, giving applications the ability to manage vastly larger datasets with lower latency than traditional storage access would allow .

The company's roadmap reveals a rapid iteration plan:

• MX1: The first generation, with working samples delivered to select partners starting in October 2025 and a production-ready version planned for 2026 .
• MX1P: An enhanced version planned for 2025 .
• MX1S: A next-generation chip with dual PCIe Gen6 x8 links, additional features, and CXL 3.2 support, slated for 2026 .

The cards support up to 256GB DDR5 DIMMs for 1TB of capacity and incorporate DDR5-8400 memory controllers . At FMS 2025 (the Future of Memory and Storage conference), the MX1 won the award for most innovative computational memory technology .

A Different Kind of Race

It's important to understand what XCENA is not doing. The company is not designing a chip to train massive foundation models faster than Nvidia's H100 or B200. The MX1 is positioned as a co-processor for data-intensive operations, working alongside existing CPUs and GPUs rather than replacing them .

For AI inference, where models must repeatedly scan large memory pools, or for database-heavy workloads like real-time analytics and vector searches, XCENA's strategy is to reduce the burden on the main processor by handling the "memory-heavy" part of the job at the source. The goal is a data center where not every piece of data needs to travel through the most expensive, power-hungry compute engines .

The $135 Million Question: Will It Work in Production?

The $570 million valuation attached to the Series B round signals strong investor conviction that memory-centric computing has a meaningful role to play in AI infrastructure . The MX1 is currently being explored with select partners to validate real-world system-level efficiency and performance gains .

However, the validation story is still being written. The FMS award and strong reported specs are promising signals, but production deployment and independent benchmarks remain the real test for a technology that proposes to re-architect a fundamental piece of the server system. XCENA's bet is that the AI industry is ready to stop moving data and start processing it where it sits.

The central idea fueling this funding is not another GPU challenger. XCENA is positioning its debut product, the MX1, as a fundamentally different category: a computational memory device that integrates processing power directly into the memory layer itself.

The Core Problem: When Data Movement Becomes the Bottleneck

In a conventional server architecture, when data needs to be processed, it makes a costly round trip from DRAM to the CPU or GPU and back again. For AI workloads — think large-scale inference, real-time analytics, and vector database queries — this constant data movement introduces latency, consumes power, and creates a well-known memory wall .

XCENA's founding insight is that many of these data-intensive operations don't actually require a GPU's specialized parallel processing. Routine filtering, searching, and analytical tasks can be handled by simpler, more power-efficient cores placed right next to the memory chips, avoiding the round trip entirely. This approach, called near-data processing (NDP), aims to offload the CPU rather than replace it .

Inside the MX1: A Server's New Secret Weapon, Not a GPU Rival

The MX1 is described as the world's first computational memory product to support both PCIe 6.0 and the CXL 3.2 standard . CXL, or Compute Express Link, provides a high-speed, low-latency pathway between processors and memory, making it the ideal backbone for a device designed to live in the memory tier .

Architecture and Key Specs

Rather than a monolithic accelerator, the MX1 is an appliance packed with thousands of custom RISC-V cores. XCENA's own documentation states these are "1,000s of 1.4GHz RISC-V cores" integrated directly into the memory subsystem . These cores can execute database-like operations (through XCENA's XFLARE software libraries) in place, processing data without moving it to the host CPU .

XCENA's technical approach uses a separate SSD-backed expansion path over PCIe 6.0, enabling what the company calls "Infinite Memory." This feature can theoretically expand a host's accessible memory pool to petabyte-scale using CXL-attached SSDs, giving applications the ability to manage vastly larger datasets with lower latency than traditional storage access would allow .

The company's roadmap reveals a rapid iteration plan:

• MX1: The first generation, with working samples delivered to select partners starting in October 2025 and a production-ready version planned for 2026 .
• MX1P: An enhanced version planned for 2025 .
• MX1S: A next-generation chip with dual PCIe Gen6 x8 links, additional features, and CXL 3.2 support, slated for 2026 .

The cards support up to 256GB DDR5 DIMMs for 1TB of capacity and incorporate DDR5-8400 memory controllers . At FMS 2025 (the Future of Memory and Storage conference), the MX1 won the award for most innovative computational memory technology .

A Different Kind of Race

It's important to understand what XCENA is not doing. The company is not designing a chip to train massive foundation models faster than Nvidia's H100 or B200. The MX1 is positioned as a co-processor for data-intensive operations, working alongside existing CPUs and GPUs rather than replacing them .

For AI inference, where models must repeatedly scan large memory pools, or for database-heavy workloads like real-time analytics and vector searches, XCENA's strategy is to reduce the burden on the main processor by handling the "memory-heavy" part of the job at the source. The goal is a data center where not every piece of data needs to travel through the most expensive, power-hungry compute engines .

The $135 Million Question: Will It Work in Production?

The $570 million valuation attached to the Series B round signals strong investor conviction that memory-centric computing has a meaningful role to play in AI infrastructure . The MX1 is currently being explored with select partners to validate real-world system-level efficiency and performance gains .

However, the validation story is still being written. The FMS award and strong reported specs are promising signals, but production deployment and independent benchmarks remain the real test for a technology that proposes to re-architect a fundamental piece of the server system. XCENA's bet is that the AI industry is ready to stop moving data and start processing it where it sits.