TSMC’s CoWoS Expansion and Intel EMIB-T: The New AI-Chip Supply Constraint

AI-chip supply is increasingly determined by what happens after a logic die leaves the wafer fab. TSMC is reportedly planning to double CoWoS advanced-packaging capacity from an estimated 130,000 wafer-equivalents per month in 2026 to about 260,000 by the end of 2028, with expansion centered on its Arizona campus and Taiwan’s AP7 facility. The estimate comes from analysts cited in Taiwanese media reporting, rather than a detailed company capacity commitment, so the final timing, product mix, and achievable output remain uncertain. 78

Why CoWoS has become an AI-chip bottleneck

CoWoS—Chip-on-Wafer-on-Substrate—is a 2.5D packaging family used to assemble large compute dies or chiplets alongside high-bandwidth memory (HBM). This type of package has to deliver dense die-to-die connections, high memory bandwidth, power delivery, and reliable manufacturing yields at a scale far beyond conventional chip packages.

For modern AI accelerators, producing the compute die is only part of the job. The chip cannot ship until its logic, HBM stacks, substrate, and package have been integrated. Advanced packaging capacity therefore becomes a hard limit on deliverable accelerators even when wafer capacity is available.

Demand is also highly concentrated. NVIDIA, Google, AMD, and Amazon collectively consumed more than 90% of global CoWoS capacity and HBM supply by value in 2025, while accounting for only about 12% of advanced logic-die production, according to Epoch AI’s analysis. 35 TrendForce likewise reported that the CoWoS shortage had spread into equipment, substrates, packaging materials, and other components. 39

That concentration helps explain why allocation matters so much. Capacity reserved by the largest customers can leave smaller AI-chip developers and new custom-accelerator programs facing long qualification and procurement timelines.

TSMC’s expansion is substantial, but forecasts vary

The 260,000-wafer-equivalent monthly figure for late 2028 represents an aggressive reported target. Other published forecasts are lower: Mizuho projected 140,000 monthly units in 2026 and 190,000 to 200,000 in 2027, while another report cited expectations of about 220,000 monthly units by the end of 2028. 64

The discrepancy is important. These are supply-chain and analyst estimates, not interchangeable measures of guaranteed output. They may also use different assumptions about CoWoS variants, outsourced production, yields, and wafer-equivalent conversion. The durable conclusion is clearer than any single forecast: TSMC and its ecosystem are expanding quickly, but demand for AI packaging is rising quickly as well.

TSMC is also building advanced-packaging capacity in Arizona while ramping additional Taiwanese sites. For now, however, advanced packaging remains heavily concentrated in Asia, and TSMC’s U.S. facilities are still part of a multiyear localization effort rather than an immediate end to Taiwan-centered supply chains. 40

How Intel EMIB-T differs from CoWoS

Intel’s Embedded Multi-die Interconnect Bridge (EMIB) takes a different physical approach. Instead of placing all dies on a full-size silicon interposer, it embeds small silicon bridges in the organic package substrate only where neighboring dies need dense, high-speed connections. 1725

EMIB-T extends that architecture with through-silicon vias in the bridge. Intel says these vertical channels deliver power directly to the chips rather than routing it around the bridge, improving power efficiency and signal delivery for complex AI packages. 25

The architectural trade-off is straightforward:

• CoWoS uses a larger interposer-based integration approach designed for high-bandwidth, large-scale packages.
• EMIB/EMIB-T uses localized bridges, reducing the amount of silicon interposer required and offering lower-cost potential if yields are comparable. 17

Intel has said EMIB-T is intended to scale beyond 12 times reticle size by 2028. 17 That makes it a meaningful option for some very large chiplet systems, particularly custom accelerators whose designers can optimize the package around a bridge-based topology.

Still, EMIB-T should not be framed as an automatic replacement for CoWoS. Packaging choices are tied to the chip’s memory arrangement, die layout, power budget, thermal design, interconnect requirements, software schedule, and supplier qualification. A customer already designed around one packaging platform cannot necessarily switch late in a product cycle.

What changes for AI-chip supply chains

Packaging capacity becomes a strategic input

AI-chip companies must secure more than leading-edge wafer starts. They need synchronized access to HBM, advanced substrates, testing, assembly, and packaging capacity. The scarcity of CoWoS means packaging allocation can shape product volumes and launch schedules just as directly as access to advanced logic nodes. 3539

This favors earlier co-design and longer-term reservations. A packaging provider is no longer simply the last manufacturing step; it becomes a core architecture and supply-planning partner.

Supply chains diversify, but Taiwan remains pivotal

The addition of TSMC capacity in Arizona and Intel’s U.S. advanced-packaging operations creates more geographic options. Intel describes its EMIB work as part of a U.S. advanced-packaging platform, while TSMC is constructing its first Arizona advanced-packaging facilities. 2540

That should reduce concentration at the margin, but not erase it. Taiwan remains central to high-volume advanced packaging, and a qualified alternative requires more than factory space: it requires process maturity, yield, materials supply, HBM integration, testing, and customer validation.

Intel, OSATs, and memory suppliers gain leverage

CoWoS constraints create an opening for Intel Foundry to sell packaging capabilities independently of a customer’s chosen logic fab. EMIB-T’s localized-bridge design gives Intel a differentiated option rather than a direct copy of CoWoS. 1725

At the same time, outsourced semiconductor assembly and test providers, substrate suppliers, and HBM manufacturers become more strategically important. The bottleneck spans a chain of interdependent inputs rather than one packaging line alone. 39

The likely outcome through the end of the decade

The most likely result is not that CoWoS disappears or that EMIB-T wins every program. It is a more segmented advanced-packaging market:

• CoWoS remains important for the largest, bandwidth-intensive accelerator packages.
• EMIB-T can serve designs that benefit from localized bridges, alternative power delivery, and potentially lower silicon-interposer use.
• 3D integration and panel-level packaging are likely to receive more attention as package dimensions, HBM counts, power requirements, and costs increase.

TSMC has been reported to be pursuing a CoPoS panel-level packaging ramp around 2028–2029, although subsequent reporting has presented a later possible timetable. 912 That uncertainty illustrates the central challenge: semiconductor packaging roadmaps are advancing rapidly, but commercialization schedules depend on manufacturing readiness as much as design ambition.

For AI-chip buyers, the practical lesson is simple: leading-edge compute is no longer procured only at the wafer level. The ability to reserve, qualify, and scale advanced packaging has become part of the competitive moat.