TSMC’s CoPoS: The Plan to Rival Samsung’s Panel-Level Packaging Dominance

The semiconductor industry is experiencing a packaging revolution, and TSMC is placing a major bet on panel-level packaging (PLP) to break Samsung's early lead and alleviate the massive capacity crunch in its workhorse CoWoS technology. At the center of this push is CoPoS, or Chip-on-Panel-on-Substrate, a new platform that replaces traditional round silicon wafers with square panels to pack more AI chips more cheaply. The pilot line is now operational, but the path to high-volume manufacturing is not yet clear.

What Makes CoPoS Different

CoPoS is TSMC's answer to the scaling limits of wafer-level packaging. Instead of processing 300 mm round wafers, it uses square panels measuring 310 mm × 310 mm and, eventually, even larger dimensions. The shift in geometry makes a surprisingly large difference: going from round to square increases usable surface area dramatically, allowing many more chips per substrate and lowering the cost per packaged chip .

The technology integrates TSMC's mature CoWoS (Chip-on-Wafer-on-Substrate) approach with Fan-Out Panel-Level Packaging (FOPLP) techniques. The result is a platform designed from the ground up for the extreme interposer sizes and chiplet integration that next-generation AI GPUs and custom ASICs demand . Nvidia is widely seen as a key early customer, with CoPoS expected to support its post-Blackwell, Rubin-era AI processors .

TSMC unveiled the 310 mm × 310 mm CoPoS product line at its 2025 North America Technology Symposium, with a target to start product shipments by the end of 2028 .

From Pilot Line to Mass Production: A Disputed Timeline

The rollout of CoPoS is unfolding on two tracks. The first is the pilot line, which has progressed on schedule. Equipment deliveries to the R&D team began in February 2026, and the full pilot line at TSMC subsidiary VisEra's Longtan plant was completed by June 2026 . At TSMC's annual shareholders' meeting on June 4, Chairman and CEO C.C. Wei publicly confirmed that the pilot line is active, materials and consumables are secured, and comprehensive equipment and process validation is underway .

The second track is volume manufacturing, and here the picture is less certain. The most commonly cited window among supply chain and industry sources is late 2028 to the first half of 2029, with large-scale production centered at TSMC's AP7 facility in Chiayi, Taiwan . Some reports even suggest shipments could begin by the end of 2028 .

However, a conflicting report from April 2026 claims that mass production has been pushed to Q4 2030—roughly two years later than many market watchers had assumed. The delay, according to the DigiTimes-cited report, stems from persistent technical challenges around "uniformity" and "warpage" when scaling to panel-level dimensions . TSMC's advanced packaging capital expenditure is still projected to grow at a 24% compound annual rate from 2025 to 2027, underscoring how central this bet has become to the company's roadmap .

Building a New Supply Chain

TSMC is not developing CoPoS in isolation. The company is actively constructing a full materials, components, and equipment supply chain, and has already started qualifying Taiwanese partners . In early 2026, Taiwan's so-called "advanced packaging national team" expanded with two new domestic firms joining the CoPoS ecosystem, signaling just how much TSMC is investing in a localized supply base to support the ramp .

The Samsung Rivalry

Samsung is the clear leader in panel-level packaging today. The company has been commercializing the technology for years, applying it to mobile processors and power management ICs, and it is now developing ultra-large-panel System-on-Panel (SoP) technology aimed at customers like Tesla . Samsung's FOPLP platform already delivers meaningful benefits over conventional packaging, such as up to a 40% smaller form factor and 15% better thermal performance .

TSMC was late to panel-level packaging, only starting serious development work in 2024 . But CoPoS represents a focused counterattack. Rather than compete directly on mobile or commodity chips, TSMC is designing CoPoS specifically for the largest, most complex AI processors—Nvidia GPUs, hyperscaler ASICs, and other high-performance computing chips that will define the next decade of data center architecture . If TSMC can solve the panel-scale engineering problems and hit a 2028–2029 mass production window, it stands to seriously erode Samsung's first-mover advantage with a platform purpose-built for the AI era.

The AI-Fueled Market at Stake

The advanced packaging market is in what analysts describe as a "golden cycle" of simultaneous volume and price growth, driven entirely by AI computing demand . The numbers tell the story:

• In 2026, the global advanced semiconductor packaging market is forecast to reach between roughly $44 billion and $59 billion, with Sigmaintell Consulting projecting $58.7 billion .
• By the early-to-mid 2030s, estimates diverge widely depending on what is included. Bloomberg Intelligence sees the 2.5D/3D packaging market alone growing at 26% annually to reach $80.5 billion by 2033 . Grand View Research forecasts a total advanced packaging market of $66 billion by 2033 at a more conservative 6% CAGR, while Fortune Business Insights projects $94.3 billion by 2034 at an 8.6% CAGR .
• The AI-chip-specific segment was valued at roughly $7.5 billion in 2025 and is expected to grow at roughly 12% annually to reach $22.5 billion by 2035 .

Despite rapid capacity expansion, 2.5D and 3D packaging supply remains persistently tight. Sigmaintell expects the imbalance to endure until at least the second half of 2027 . CoPoS is TSMC's long-term answer to that shortfall—a way to break through the wafer-level ceiling and unlock capacity that the current CoWoS infrastructure simply cannot provide.

A Defining Unresolved Question

The biggest variable in this entire roadmap is engineering, not market demand. Whether TSMC can solve the panel-level uniformity and warpage issues that have dogged early development will determine if CoPoS arrives as a powerful new competitor at the end of this decade, or slips toward 2030 . As things stand in mid-2026, the pilot line is complete, the supply chain is forming, and the money is committed. The rest depends on the yield curves TSMC can extract from square panels.