Inside the Cadence-Samsung 2nm Chip Deal: SF2P, Nvidia, and the Race to Power Physical AI

As the semiconductor industry races to keep pace with AI's insatiable appetite for computing power, two foundational players are cementing a deeper alliance. At the SAFE Forum 2026 on May 28 in San Jose, Cadence Design Systems and Samsung Foundry announced a significant expansion of their multi-year collaboration, directly targeting the next wave of AI infrastructure and Physical AI. The new pact centers on Samsung's second-generation 2nm process (SF2P), advanced 3D-IC packaging, and deep integration of Nvidia's interconnect technology, creating a signoff-ready platform for the world's most complex chip designs .

A Foundation on SF2P, SF4X, and SF5A Nodes

The cornerstone of this expanded partnership is a new multi-year IP agreement that broadens Cadence's memory and interface IP portfolio across three of Samsung's advanced process nodes: SF4X, SF5A, and the flagship SF2P (second-generation 2nm) . This isn't just a single-node play; the multi-node scope signals a strategic commitment to support a wide range of applications from high-performance data center silicon to automotive-grade chips.

For the cutting-edge SF2P node, the IP portfolio is comprehensive and high-performance, including:

• High-speed SerDes
• PCIe and UCIe (Universal Chiplet Interconnect Express) for chiplet-based designs
• Major memory interfaces like LPDDR6/5x, GDDR7, and DDR5

The SF4X node separately gets a robust lineup including LPDDR6/5x-14.4G, GDDR7-36G, DDR5-9600, and PCIe 6.0/5.0/CXL 3.2, underscoring the breadth of the collaboration .

Nvidia's Direct Integration: NVLink-C2C and CUDA-X

A standout detail of the SAFE 2026 announcement is the explicit incorporation of Nvidia's technology into the joint design flow. The collaboration integrates NVIDIA NVLink-C2C—a high-bandwidth, low-latency chip-to-chip interconnect—directly into Cadence's EDA and system design and analysis (SDA) flows on Samsung's SF2P process. This is paired with CUDA-X GPU-accelerated libraries, optimizing the entire design flow for agentic AI and next-generation AI architectures .

The inclusion of Nvidia's technology is strategic. Nvidia is leveraging the combined Cadence-Samsung platform itself to optimize its future AI architectures and high-bandwidth interconnects. This creates a virtuous cycle where the design tool ecosystem is battle-hardened by one of the world's most demanding AI hardware companies, providing customers with a platform that is already being proven on the most aggressive silicon roadmaps .

Scaling AI with 3D-IC and 3D Cube-H

As chip scaling becomes more challenging, moving into the third dimension is critical. Cadence is delivering a fully certified reference flow for Samsung's 3D Cube-H advanced packaging technology. This is not a theoretical roadmap item but a production-ready suite that tackles the hardest physical design challenges:

• Hybrid Copper Bonding (HCB) support for ultra-dense vertical connections
• Silicon interposer auto-routing for complex multi-chiplet integration
• An integrated tool chain featuring the Integrity 3D-IC Platform, Innovus, Voltus, and Pegasus for everything from floorplanning and implementation to physical verification and signoff

The certified flow directly addresses the practical obstacles of 3D-IC design with specific enhancements for power integrity, thermal and warpage analysis, and glitch power optimization. These are the exact signoff concerns that can delay tape-outs on bleeding-edge multi-die packages .

Ambarella: The First 2nm Edge AI Customer

The partnership already has a named customer putting the platform to the test. Ambarella, a leader in edge AI vision processors, is the public early adopter of this ecosystem. The company is developing a next-generation 2nm edge AI platform targeting robotics, drones, autonomous machines, and advanced sensing applications .

Ambarella is implementing Cadence's PCIe 5.0 IP on the SF2P node and has publicly stated that the collaboration is essential for managing the significant design, verification, and manufacturing complexities specific to this advanced node. The choice of 2nm for edge AI applications rather than just massive data center GPUs is a strong signal that the SF2P platform is being positioned for a diverse range of power and performance profiles .

The Bigger Picture: Competing for AI Infrastructure Dominance

The SAFE 2026 announcement, under the theme "The Nexus for Silicon Intelligence," is a direct response to the explosive demand for AI infrastructure and Physical AI across data centers, edge devices, and intelligent systems . Both Cadence and Samsung frame this collaboration as a way to enable customers to deliver next-generation AI and HPC systems faster by providing a signoff-ready, production-verified platform that combines cutting-edge process technology, 3D-IC integration, and GPU-accelerated design flows .

By tightly integrating IP, EDA tools, Nvidia's interconnect, and advanced packaging into a single certified flow, Cadence and Samsung are removing the fragmented risk that often plagues early node adoption. The partnership positions Samsung Foundry as a formidable alternative in the 2nm race, providing a turnkey ecosystem that directly competes for the next generation of AI silicon designs.