Samsung’s Vertical Leap: Inside the First 3D Stacked Transistor with a Record 42nm Gate Pitch

Samsung’s innovation is to sidestep the problem entirely. Instead of placing NMOS and PMOS transistors next to each other, the new 3DSFET architecture stacks them vertically. This means the critical isolation layer between the two types of transistors becomes a vertical structure, which consumes no additional surface area on the chip. In theory, this approach can double transistor density within the same footprint without pushing against the limits of horizontal isolation .

The Core Innovations: Triple-Stacked Nanosheets and a 42nm Record

The practical implementation of this vertical vision is a feat of materials science and precision engineering. Samsung’s team didn’t just stack two simple transistors on top of each other. Their 3DSFET uses triple-stacked nanosheet channels for both the upper (P-type) and lower (N-type) transistors, for a total of six nanosheets on a single wafer. This represents the largest number of stacked nanosheets ever demonstrated in a 3D stacked FET or complementary FET (CFET) . The nanosheet architecture already provides superior electrostatic control over current, and combining it with vertical stacking creates a powerful synergy for performance and power efficiency.

To achieve this, the engineers had to solve the critical challenge of electrical isolation. The vertically adjacent transistors require a perfect insulating barrier to function independently. The team introduced a high-quality intermediate dielectric layer between the upper and lower devices. This vertical insulator is the key that unlocks the dense integration, eliminating the crosstalk that would otherwise make the design non-functional .

The result is a fully operational device with a gate pitch of 42nm, the smallest on public record. Wookhyun Kwon, an expert from Samsung’s Logic TD team, clarified that while previous research has reported smaller dimensions, the 42nm figure is the smallest ever achieved in a fabricated transistor structure .

Award-Winning Validation

The significance of this work was immediately recognized by the academic and industry community at the VLSI Symposium, one of the world’s top three semiconductor conferences. The paper, titled "First Demonstration of 3D Stacked FETs at Gate Pitch of 42 nm Featuring Triple Stacked Nanosheet Channels for Advanced Logic Applications" and authored by Donghoon Hwang and colleagues, achieved a review score of 8.29 out of 10, the highest among all submissions . This exceptional score earned it both the Best Paper Award and designation as a Technology Highlight of the symposium .

The Road Ahead for AI and HPC Chips

Samsung envisions the 3DSFET architecture as a foundational technology for the future of high-performance logic semiconductors, specifically targeting the extreme demands of next-generation AI and high-performance computing (HPC) applications where transistor density is a critical performance lever .

However, it’s essential to view this as a monumental proof-of-concept rather than a product announcement. The work currently exists at the demonstration stage. Samsung’s Logic TD Team has stated that it will continue research with the goal of eventual commercialization, but no volume production timeline has been specified. Significant development remains to turn this single-device demonstration into a high-yield, mass-manufacturable process . Despite the long road ahead, Samsung has provided a concrete and validated answer to the question of what comes after the nanosheet era: going up.