Samsung’s 3-Phase HBM Roadmap: From 4nm Base Dies to zHBM 3D Memory

Samsung’s HBM strategy is evolving in three steps: first, move memory-control and interface functions into the HBM base die; next, add monitoring, expansion and near-memory processing; finally, place the AI processor directly beneath the DRAM stack in a true 3D package. The long-term destination is zHBM, but Samsung’s headline performance figures are targets for a future architecture—not demonstrated production benchmarks. 1713

The roadmap in one view

Phase	Main architectural change	Intended benefit
Phase 1: custom HBM (cHBM)	Move the memory controller and a more compact die-to-die interface into the HBM logic base die	Reclaim accelerator silicon and reduce interface-related data-movement cost
Phase 2: advanced HBM (aHBM)	Add telemetry, memory-expansion controllers and selected processing elements to the base die	Improve memory management, capacity and utilization near the data
Phase 3: zHBM	Stack the DRAM/HBM structure directly above the AI accelerator	Shorten the processor-memory path and increase vertical connectivity

The progression matters because it changes the role of the base die. Instead of serving mainly as a connection and control layer, it becomes an increasingly capable logic subsystem—and eventually part of a vertically integrated compute-memory structure. 182027

Phase 1: cHBM moves control functions off the accelerator

Samsung’s HBM4 starting point combines 1c DRAM with a 4nm logic base die. Samsung says the HBM4 design can reach up to 13 Gbps and up to 3,300 GB/s of bandwidth per stack, although those are HBM4 product claims rather than specifications for the later zHBM concept. 3537

The first roadmap phase builds on that logic capability by replacing the conventional, larger HBM PHY on the AI accelerator with a more compact die-to-die interface. It also moves memory-controller functions from the accelerator to the HBM base die. 1720

That creates two potential advantages:

• More accelerator area: Silicon previously used for memory-control and interface functions could instead support compute, cache or application-specific logic.
• A shorter electrical path: Moving functions into the base die can reduce the distance and overhead associated with communication between the accelerator and HBM, improving interface energy efficiency. 13

Some reports cite a possible 5%–10% recovery of accelerator area and a 10%–20% performance improvement, but those figures come from reported roadmap material and should not be treated as a universal result for every AI processor. 1729

Phase 2: aHBM makes the base die an active subsystem

The second phase adds functionality to the silicon freed up in the base die. Samsung’s aHBM concept includes sensors and real-time telemetry for conditions such as temperature and voltage, along with reliability and self-test functions. That information could allow the system to respond more precisely to operating conditions and improve monitoring of the memory stack. 182728

The base die could also act as a memory-expansion interface, connecting additional HBM or other memory such as LPDDR. This would give system designers another way to expand usable memory capacity without relying solely on the local HBM stack. 182829

Samsung has also proposed putting processing elements in the base die. These would not replace a general-purpose GPU or accelerator. Their more limited role would be to handle selected, memory-intensive operations close to the data, reducing some traffic across the package and potentially improving utilization. 61927

This is the transitional stage of the roadmap: HBM remains beside the processor in a 2.5D package, but the base die begins to behave more like an intelligent I/O and processing subsystem.

Phase 3: zHBM stacks memory directly above compute

zHBM is the most radical step. In a conventional HBM package, the accelerator and HBM stacks sit side by side on an interposer. Samsung’s zHBM concept instead places the processor directly beneath the DRAM stack, creating a true 3D compute-memory structure. 3732

The vertical arrangement is intended to shorten the route data must travel and replace a large edge-oriented interface with denser, distributed vertical connections. In principle, that could deliver:

• higher bandwidth through a much wider connection,
• lower I/O power because signals travel a shorter distance,
• more efficient data delivery for AI training and inference, and
• a smaller lateral package footprint because HBM no longer has to sit around the processor. 13732

This is why zHBM is more than simply “faster HBM.” It changes the physical relationship between memory and compute. The expected benefit depends not only on DRAM speed, but also on package topology, interface design, power delivery and the workload’s sensitivity to data movement.

How the targets compare with HBM5

Samsung’s published and reported targets use different baselines and metrics. They should therefore be read as separate claims, not as one directly comparable benchmark:

• HBM5 versus HBM4E: Samsung is targeting 2× performance, 20% higher performance per watt and 20% lower thermal resistance. Reports place mass production around 2028, but HBM5 remains a roadmap generation rather than a broadly established production standard. 4101214
• zHBM versus HBM4E: A Hot Chips-oriented comparison reported about 70% lower DRAM power and more than 2.3× DRAM bandwidth. 111
• Longer-range zHBM targets: Samsung has also presented goals of up to 8× performance, 3× performance per watt and a 75%–90% reduction in thermal resistance compared with HBM4E. 21314

The difference between “2.3× bandwidth” and “8× performance” is not automatically contradictory. Bandwidth, DRAM power, application performance and performance per watt measure different things and may use different configurations. Samsung has not published enough methodology in the supplied material to independently reconcile every figure, so the numbers should be treated as architecture targets rather than a single benchmark result. 11014

Why the roadmap fits Samsung’s CUBE strategy

Samsung describes CUBE as an approach organized around four goals: Capacity, Utilization, Bandwidth and Efficiency. The company’s argument is that AI systems need more than progressively faster memory interfaces; they also need memory to be placed and used more intelligently in three dimensions. 257

The three HBM phases map onto those goals:

• Capacity: Memory expansion through the base die could connect additional memory tiers, while vertical stacking increases density without expanding the package laterally. 418
• Utilization: Telemetry, control logic and selective near-memory processing could make existing memory capacity and bandwidth more useful for particular workloads. 1827
• Bandwidth: Direct vertical connections reduce the physical distance between compute and memory and create room for denser I/O. 37
• Efficiency: Cutting data movement and interface overhead could reduce power, while better thermal monitoring could help systems operate closer to their limits. 1511

zHBM is therefore the clearest expression of Samsung’s Z-axis memory approach: build upward to increase density and reduce communication distance, rather than continuing to expand a side-by-side 2.5D package. 713

The engineering problems Samsung still has to solve

Thermal management

Putting a high-power processor beneath a DRAM stack makes heat removal more difficult because the compute die is farther from the cooling path, while DRAM must remain within a relatively constrained thermal operating range. Samsung’s reported reduction in thermal resistance is consequently a design target, not an automatic benefit of 3D stacking. The company and its manufacturing partners will need to demonstrate that performance, memory reliability and cooling requirements can coexist in a production package. 1419

Bonding, alignment and yield

A direct 3D structure requires extremely precise bonding and alignment across large interfaces. Wafer thinning, TSV integration, warpage control, defect management and high-yield bonding all become more important as the processor and memory are physically joined. A defect in either side of the package can affect the value of the complete assembly, increasing the importance of known-good-die testing, repair mechanisms and post-bond test access. Samsung’s roadmap already points to expanded reliability and self-test functions in the base die, underscoring how closely packaging and test are linked to the architecture. 2728

Power delivery and signal integrity

A very wide vertical interface still needs stable power delivery, timing, clocking and noise control. Higher theoretical bandwidth does not guarantee higher application performance if power integrity, thermal throttling or signal quality limits sustained operation.

Stack height and mechanical constraints

Adding more vertical structure can increase package thickness, mechanical stress and cooling-path complexity. The final design must balance capacity and bandwidth against stack height, warpage, manufacturability and the limits of the substrate and system board.

Processor-memory co-design

Standard HBM can be integrated as a relatively modular memory component. aHBM and especially zHBM require tighter coordination among the accelerator, base-die logic, package, firmware, runtime and software stack. Interfaces, control ownership, coherency, fault handling and near-memory operations must be designed together. That can improve specialization, but it may also make the resulting system less interchangeable than conventional HBM-based designs.

Commercial timing and ecosystem adoption

zHBM remains a future concept, and reports place commercialization after 2029. Its schedule and performance claims depend on packaging maturity, customer adoption, standards, yield and cost. 8914

The practical takeaway

Samsung’s roadmap is best understood as a gradual transfer of intelligence toward the memory stack:

1. cHBM is mainly about reclaiming accelerator area and offloading interface and control work.
2. aHBM turns the base die into a monitored, expandable and selectively programmable memory subsystem.
3. zHBM fuses compute and memory physically by placing the processor beneath the DRAM stack.

The potential payoff is substantial: less I/O power, more effective accelerator silicon, denser bandwidth and better performance per watt. But the final phase also shifts the hardest problems from memory-interface design to thermal engineering, bonding, yield, testing and system co-design. For now, zHBM is an ambitious direction backed by targets—not yet proof that a production 3D AI package can deliver them.