Nvidia Feynman: Why TSMC’s A16, SoIC and CPO Capacity Matter

The reported process choice is TSMC’s A16, described in the coverage as an enhanced 2nm-class or 1.6nm-class process. Feynman would therefore reportedly skip the N2 family rather than use it as an intermediate generation.

That combination could improve density and help manage the power and signal-integrity challenges of very large AI clusters. However, the sources do not provide verified final performance specifications, so claims about exact Feynman bandwidth or performance should not be treated as confirmed product figures.

What TSMC would need to provide

Feynman’s reported requirements extend well beyond additional leading-edge wafer starts. TSMC would need to coordinate several manufacturing layers at once:

• A16 logic production: TSMC would need to bring the A16 process to the yield and volume levels required for a high-volume Nvidia platform. Reports identify A16 as Feynman’s expected process technology, but customer allocation and final production details remain unconfirmed.
• SoIC 3D integration: More vertically stacked chiplets would require substantially greater SoIC throughput, along with the bonding, testing, thermal-management and yield-control capabilities needed to make the process economical at scale.
• HBM and 2.5D packaging: The platform is expected to combine 3D integration with HBM and related advanced-packaging flows such as CoWoS or successor technologies. The reporting does not establish a final Feynman package configuration.
• CPO manufacturing: Optical engines and switching silicon would need to be integrated and tested as a reliable production system rather than as a limited demonstration. TSMC is reported to be involved in the silicon-photonics and packaging chain for Nvidia’s CPO products.

The strategic implication is that packaging capacity could become as important to Nvidia’s roadmap as transistor capacity. A fab can produce advanced logic, but a complete AI platform also depends on assembling dies, memory and optical connections with acceptable yields and power characteristics.

SoIC capacity: the reported ramp

Supply-chain reports describe a sharp expansion in TSMC’s SoIC plans. Earlier targets cited in the reporting called for roughly 10,000 to 15,000 SoIC wafers per month during 2026, rising to 20,000 wafers per month by the end of that year. The newer reported target is approximately 50,000 wafers per month by the end of 2027.

That would represent a 2.5-fold increase from the 20,000-wafer end-2026 target in the following year. The demand is reportedly linked not only to Nvidia but also to AMD and other advanced-packaging customers, so the full capacity would not necessarily be dedicated to Feynman.

These are reported planning figures, not confirmed Nvidia allocations. They also describe wafer capacity rather than finished Feynman systems; actual product output would depend on die sizes, package designs, yields and downstream testing.

AP7 and AP8: where the packaging expansion is taking shape

The reported facility build-out centers on TSMC’s Chiayi AP7 and AP8 in the Southern Taiwan Science Park.

AP7 is described as an eight-phase project. Reporting says its early phases include installation activity, with later phases at different stages of permitting and planning. The facility is expected to support multiple advanced-packaging technologies, including SoIC, CoWoS and CPO-related production, depending on customer requirements.

AP8 is described as a three-phase project, P1 through P3, with a focus on advanced packaging such as CoWoS. Public reports do not provide sufficiently reliable phase-by-phase commissioning dates to treat every construction milestone as a firm production deadline.

The important point is timing: packaging plants and equipment must be planned well before a new accelerator reaches volume production. If Feynman is targeted for the second half of 2028, qualification and capacity decisions would need to happen years earlier.

Nvidia is ramping Rubin while preparing Feynman

The transition is not a clean handoff. Nvidia is reportedly ramping Vera Rubin into mass production while shifting research and supply-chain resources toward Feynman. Nvidia’s own product materials describe Vera Rubin as entering full production, while industry reports place Feynman’s target in the second half of 2028.

That overlap creates both an opportunity and a manufacturing burden. Nvidia can maintain a regular product cadence instead of waiting for one generation to finish before preparing the next. TSMC and its suppliers, however, must support current Rubin demand while qualifying a new process, more complex packaging, optical components and associated materials for Feynman.

Why Nvidia’s CPO switch matters

Nvidia’s Spectrum-X Ethernet Photonics platform provides an early example of the direction Feynman is reported to take. The product integrates co-packaged optics directly with the switching ASIC, placing optical components close to the silicon to reduce the distance that high-speed signals travel through electrical connections. Nvidia says the platform has reached production through co-engineering across the semiconductor and systems ecosystem.

Nvidia describes Spectrum-X Ethernet Photonics as a 200G-per-lane CPO Ethernet system, with up to 409.6 Tb/s of bandwidth in its product materials. Its product page lists availability in the second half of 2026, while industry reporting has described shipments to selected partners and a move into volume production.

The reported supply chain assigns TSMC a silicon-photonics manufacturing role and Foxconn responsibility for finished switch-system assembly. Other partners are involved in chip-level packaging, testing, lasers and optical subassemblies.

CPO matters because AI clusters are increasingly constrained by the network between accelerators. As systems scale, power consumption, bandwidth, electrical reach and signal integrity can limit overall performance even when the compute silicon itself becomes faster. Optical integration is intended to address part of that scale-out problem, although production volume, reliability and customer deployment remain important practical tests.

What the roadmap means for AI infrastructure

Feynman’s reported design points to a broader change in how AI hardware capacity is planned. Nvidia’s roadmap can influence TSMC’s capital spending before a product ships because the platform requires coordinated investment in logic, memory integration, 3D stacking, optical packaging, equipment and testing.

Three consequences stand out:

1. Advanced packaging becomes a strategic constraint. The reported move from 20,000 to 50,000 SoIC wafers per month suggests that 3D integration capacity may be as critical as leading-edge wafer supply.
2. The supplier ecosystem becomes more tightly coupled to Nvidia’s cadence. Earlier construction and equipment installation are necessary because packaging capacity cannot be added instantly after an accelerator generation begins shipping.
3. Cloud operators must fund complete AI systems. A 2028-era deployment would require more than accelerators: it would also depend on HBM-equipped systems, advanced packages, optical fabrics, power delivery and cooling. This is an inference from the reported technology direction, not a disclosed forecast of cloud spending.

Feynman therefore matters as a supply-chain signal as much as a future chip name. If the reports are accurate, Nvidia is asking TSMC to deliver a synchronized manufacturing platform in which A16 logic, SoIC stacking, HBM integration and CPO networking mature together. The resulting bottleneck may not be the smallest transistor alone, but the industry’s ability to assemble and connect enormous AI systems reliably at scale.