The exact design remains unknown. AMD’s role could involve CPU intellectual property, chiplet integration, packaging, interconnects, or another part of the program. No supplied source establishes whether AMD would design a complete TPU, provide specific IP, or participate only in package development.

Why AMD is a technically credible partner

AMD has a relevant commercial precedent in the Instinct MI300A. AMD describes the device as combining 24 Zen 4 x86 CPU cores, 228 CDNA 3 GPU compute units, and 128 GB of unified HBM3 memory in a coherent package.

That architecture demonstrates AMD’s experience combining general-purpose computing, accelerator resources, and high-bandwidth memory in one system. It also makes AMD a credible candidate for a design in which CPU and accelerator resources need to exchange data with less movement between separate components.

But the MI300A is not evidence that Google’s rumored TPU would use AMD’s exact CPU cores, memory system, packaging technology, or software stack. It is a capability reference—not confirmation of the alleged project.

Why reinforcement learning and agentic AI change the hardware question

Traditional AI accelerator discussions often focus on matrix throughput and memory bandwidth. Agentic systems add a wider range of tasks around the model: coordinating steps, managing tools, evaluating intermediate results, and responding to changing environments. Reinforcement-learning workloads likewise combine accelerator-heavy computation with general-purpose processing.

That creates a potential bottleneck when a server has too few CPU resources relative to its accelerators. One possible response is to increase the CPU-to-accelerator ratio; another is to bring some CPU capability into the accelerator package. Reports characterize the rumored TPU v10 direction in those terms, but the reported ratios and final architecture should not be treated as confirmed Google specifications.

Google’s supplier strategy is becoming more distributed

The AMD rumor fits a broader reported expansion of Google’s custom-silicon ecosystem. Broadcom has been described as Google’s principal TPU implementation partner, contributing to physical design, high-speed interfaces, power delivery, and packaging or manufacturing coordination.

MediaTek was separately reported to be joining Google on a seventh-generation TPU while Google retained its relationship with Broadcom. In those reports, Google led the core architecture and MediaTek handled I/O and peripheral-related work, with production expected at TSMC in 2026.

The important implication is that additional suppliers do not automatically replace existing ones. Google can divide work by generation, training versus inference, chiplet, I/O function, packaging requirement, or available production capacity. A future AMD role would therefore be more consistent with a multi-partner strategy than with proof that Broadcom or MediaTek had been displaced.

The Marvell agreement is confirmed—but it is different evidence

Google’s expanded Marvell relationship provides a disclosed commercial data point, unlike the AMD report. The agreement covers custom semiconductor programs that attach to the TPU ecosystem, including areas such as AI inference accelerators, storage controllers, network-interface controllers, memory-interface controllers, and near-memory compute.

Marvell issued Google a warrant to purchase up to 58,970,907 shares at $206.58 per share—worth approximately $12.2 billion if fully exercised.

That figure should be read carefully. The warrant is tied to future purchasing targets, with shares vesting in tranches associated with Marvell revenue from Google. Reports describe a potential purchasing framework of up to $120 billion through fiscal 2033, but that is a target-dependent ceiling, not an unconditional order or immediate revenue commitment.

The Marvell deal supports the broader conclusion that Google is building a deeper and more diversified custom-chip supply chain. It does not confirm AMD’s rumored TPU v10 involvement.

What the rumor could mean for AMD

If the project exists and reaches meaningful production, it could give AMD a new path into hyperscaler custom silicon. That would extend its AI opportunity beyond selling Instinct accelerators and EPYC CPUs, potentially turning its CPU IP and packaging capabilities into part of a customer-specific system.

The financial case is still entirely speculative. The available reporting does not disclose the scope of AMD’s work, economics, intellectual-property ownership, manufacturing partner, packaging capacity, expected volumes, or timing. There is therefore no sound basis for treating the rumor as booked AMD revenue or assigning a specific valuation impact to it.

What it could mean for Google and its existing partners

For Google, using more suppliers could provide additional design capacity, manufacturing flexibility, and negotiating leverage while allowing specialized components to be matched with the partners best suited to build them. It may also help Google tailor different accelerators to training, inference, and agentic workloads.

For Broadcom and MediaTek, the possibility of another partner could introduce competitive pressure at the margin. But it would be premature to infer lost Broadcom business, a reduction in MediaTek’s role, or a change in TPU market share. Google’s reported supply-chain pattern already suggests that multiple partners can work on different portions of the roadmap at the same time.

Why a TPU v10 launch would likely be years away

Even the reported TPU roadmap places an advanced-node TPU v8 program in production only in late 2027. A v10 product would come later still, assuming the numbering and roadmap reports are accurate.

A heterogeneous TPU would also require more than an architectural announcement. Google and its partners would need to define the CPU–accelerator interface, validate memory coherency and packaging, complete physical design, enable the compiler and software stack, secure fabrication and advanced-packaging capacity, test the silicon, and deploy it in data centers.

Those steps make a near-term TPU v10 launch unlikely. The prudent conclusion is a multi-year, post-v8 horizon—not a confirmed production date.

Bottom line

The strongest confirmed signal is Google’s continued expansion of its custom-chip supplier network, including the disclosed Marvell agreement. The AMD–TPU v10 claim is weaker: it comes from attributed market chatter and has not been confirmed by either company.

The rumor is technically interesting because it connects AMD’s CPU and packaging experience with AI workloads that may need more general-purpose compute around the accelerator. But until Google or AMD discloses a program, investors and customers should treat the architecture, commercial value, production timing, and competitive impact as open questions.

The exact design remains unknown. AMD’s role could involve CPU intellectual property, chiplet integration, packaging, interconnects, or another part of the program. No supplied source establishes whether AMD would design a complete TPU, provide specific IP, or participate only in package development.

Why AMD is a technically credible partner

AMD has a relevant commercial precedent in the Instinct MI300A. AMD describes the device as combining 24 Zen 4 x86 CPU cores, 228 CDNA 3 GPU compute units, and 128 GB of unified HBM3 memory in a coherent package.

That architecture demonstrates AMD’s experience combining general-purpose computing, accelerator resources, and high-bandwidth memory in one system. It also makes AMD a credible candidate for a design in which CPU and accelerator resources need to exchange data with less movement between separate components.

But the MI300A is not evidence that Google’s rumored TPU would use AMD’s exact CPU cores, memory system, packaging technology, or software stack. It is a capability reference—not confirmation of the alleged project.

Why reinforcement learning and agentic AI change the hardware question

Traditional AI accelerator discussions often focus on matrix throughput and memory bandwidth. Agentic systems add a wider range of tasks around the model: coordinating steps, managing tools, evaluating intermediate results, and responding to changing environments. Reinforcement-learning workloads likewise combine accelerator-heavy computation with general-purpose processing.

That creates a potential bottleneck when a server has too few CPU resources relative to its accelerators. One possible response is to increase the CPU-to-accelerator ratio; another is to bring some CPU capability into the accelerator package. Reports characterize the rumored TPU v10 direction in those terms, but the reported ratios and final architecture should not be treated as confirmed Google specifications.

Google’s supplier strategy is becoming more distributed

The AMD rumor fits a broader reported expansion of Google’s custom-silicon ecosystem. Broadcom has been described as Google’s principal TPU implementation partner, contributing to physical design, high-speed interfaces, power delivery, and packaging or manufacturing coordination.

MediaTek was separately reported to be joining Google on a seventh-generation TPU while Google retained its relationship with Broadcom. In those reports, Google led the core architecture and MediaTek handled I/O and peripheral-related work, with production expected at TSMC in 2026.

The important implication is that additional suppliers do not automatically replace existing ones. Google can divide work by generation, training versus inference, chiplet, I/O function, packaging requirement, or available production capacity. A future AMD role would therefore be more consistent with a multi-partner strategy than with proof that Broadcom or MediaTek had been displaced.

The Marvell agreement is confirmed—but it is different evidence

Google’s expanded Marvell relationship provides a disclosed commercial data point, unlike the AMD report. The agreement covers custom semiconductor programs that attach to the TPU ecosystem, including areas such as AI inference accelerators, storage controllers, network-interface controllers, memory-interface controllers, and near-memory compute.

Marvell issued Google a warrant to purchase up to 58,970,907 shares at $206.58 per share—worth approximately $12.2 billion if fully exercised.

That figure should be read carefully. The warrant is tied to future purchasing targets, with shares vesting in tranches associated with Marvell revenue from Google. Reports describe a potential purchasing framework of up to $120 billion through fiscal 2033, but that is a target-dependent ceiling, not an unconditional order or immediate revenue commitment.

The Marvell deal supports the broader conclusion that Google is building a deeper and more diversified custom-chip supply chain. It does not confirm AMD’s rumored TPU v10 involvement.

What the rumor could mean for AMD

If the project exists and reaches meaningful production, it could give AMD a new path into hyperscaler custom silicon. That would extend its AI opportunity beyond selling Instinct accelerators and EPYC CPUs, potentially turning its CPU IP and packaging capabilities into part of a customer-specific system.

The financial case is still entirely speculative. The available reporting does not disclose the scope of AMD’s work, economics, intellectual-property ownership, manufacturing partner, packaging capacity, expected volumes, or timing. There is therefore no sound basis for treating the rumor as booked AMD revenue or assigning a specific valuation impact to it.

What it could mean for Google and its existing partners

For Google, using more suppliers could provide additional design capacity, manufacturing flexibility, and negotiating leverage while allowing specialized components to be matched with the partners best suited to build them. It may also help Google tailor different accelerators to training, inference, and agentic workloads.

For Broadcom and MediaTek, the possibility of another partner could introduce competitive pressure at the margin. But it would be premature to infer lost Broadcom business, a reduction in MediaTek’s role, or a change in TPU market share. Google’s reported supply-chain pattern already suggests that multiple partners can work on different portions of the roadmap at the same time.

Why a TPU v10 launch would likely be years away

Even the reported TPU roadmap places an advanced-node TPU v8 program in production only in late 2027. A v10 product would come later still, assuming the numbering and roadmap reports are accurate.

A heterogeneous TPU would also require more than an architectural announcement. Google and its partners would need to define the CPU–accelerator interface, validate memory coherency and packaging, complete physical design, enable the compiler and software stack, secure fabrication and advanced-packaging capacity, test the silicon, and deploy it in data centers.

Those steps make a near-term TPU v10 launch unlikely. The prudent conclusion is a multi-year, post-v8 horizon—not a confirmed production date.

Bottom line

The strongest confirmed signal is Google’s continued expansion of its custom-chip supplier network, including the disclosed Marvell agreement. The AMD–TPU v10 claim is weaker: it comes from attributed market chatter and has not been confirmed by either company.

The rumor is technically interesting because it connects AMD’s CPU and packaging experience with AI workloads that may need more general-purpose compute around the accelerator. But until Google or AMD discloses a program, investors and customers should treat the architecture, commercial value, production timing, and competitive impact as open questions.