What Intel’s Panther Lake Teardown Reveals About 18A

SemiAnalysis’s teardown of Intel’s Core Ultra 7 365 offers a close look at 18A in a commercial processor: the compute tile uses RibbonFET gate-all-around transistors and PowerVia backside power delivery. It also shows why Panther Lake is not an all-18A chip—and why a successful product implementation does not, by itself, establish a process lead over TSMC or Samsung. 12

What the teardown shows inside Intel 18A

The cross-sections show RibbonFETs with four stacked horizontal silicon sheets, with the gate surrounding each channel. Intel’s PowerVia approach routes power through a dedicated backside metal network and nano-through-silicon vias. That frees front-side wiring resources that would otherwise be used for power delivery. 34

These structures are significant integration choices, not a free performance gain. The teardown describes trade-offs that include additional capacitance, thermal resistance and process complexity. The cross-sections reveal how Intel built the device, but do not establish a product-level performance or temperature advantage over competing designs. 4

Panther Lake uses several process nodes

Panther Lake combines three active tiles on a passive base tile using Intel’s Foveros-S packaging. The compute tile is made on Intel 18A. The graphics tile varies by configuration: the smaller GT1 option uses Intel 3, while the larger GT2 option uses TSMC N3E. The I/O tile uses TSMC N6. 12

That division matters when interpreting the chip. Panther Lake demonstrates 18A on the compute tile, not across every part of the package. The compute tile includes CPU cores, an NPU, media engines and memory-side cache, while graphics and I/O remain on separate tiles. 34

How 18A’s measured logic density compares

SemiAnalysis measured Panther Lake’s 18A compute logic and the package’s TSMC N3E graphics logic at similar logic density. Its comparison also found that 18A did not lead the reported peak-density results for TSMC N3P, TSMC N2 or Samsung SF2. These measurements compare particular logic regions; they should not be treated as a complete ranking of every feature or product built on those process nodes. 2

RibbonFET and Samsung’s MBCFET: structural differences, not a thermal verdict

Intel’s RibbonFET and Samsung’s MBCFET are both gate-all-around, nanosheet transistor designs. The teardown describes Intel’s four-sheet structure and its combination with backside power delivery. It contrasts that with Samsung SF2’s front-side power arrangement and different contact and interconnect materials. 34

Those structural differences help explain that the companies made different integration choices. They do not, on their own, show which chip runs cooler or performs better: the teardown’s discussion of thermal resistance is a process trade-off, not a direct thermal comparison between finished Intel and Samsung products. 4

What manufacturing signals do—and do not—show

Intel and ASML report that more than one million wafers have been processed using High-NA EUV across tool certification, research and development, and production. High-NA is used on selected layers of some Panther Lake processors. The cumulative total is evidence of experience with the equipment, not a count of finished Panther Lake wafers or wafers patterned entirely with High-NA. 19

A separate report puts EXE:5200B throughput at 175 wafers per hour in one mode and about 125 when stitching is required. That illustrates a throughput trade-off for stitching; it is not, by itself, a measure of Intel’s overall manufacturing cost or output. 22

An analyst estimate puts 18A yield at roughly 80%, but the measurement basis is not disclosed and Intel has not published an absolute yield figure. The estimate therefore cannot establish yield across all 18A production or cost parity with competitors. 24

Wildcat Lake points to another design choice: its reported compute die is 38% smaller than Panther Lake’s, and it uses an organic multi-chip package instead of Foveros. That extends the range of products using related technology, but neither the smaller die nor Panther Lake’s teardown proves that Intel has overtaken competing nodes in density, manufacturing economics or high-end graphics production. 5

The takeaway

Panther Lake is concrete evidence that Intel has integrated RibbonFETs and PowerVia into a commercial processor and combined an 18A compute tile with tiles made on other processes. The strongest caveat is equally concrete: 18A’s measured logic density was comparable to N3E in the teardown, not ahead of every competing node. High-NA experience and reported yield estimates indicate progress, but the available figures leave important questions about yield scope, throughput and competitiveness unanswered. 2192224