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Waymo’s 5nm CarTPU: Inside the Sensor-Fusion Processor Powering Its Robotaxis
Waymo’s first custom self driving ASIC is a 5nm sensor fusion front end—not a replacement for the main Waymo Driver computer. The reported package measures 45 × 45 mm, contains a 208 mm² die, uses in package LPDDR5X at 273 GB/s, and consumes less than 75 watts.
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Key takeaways
- Waymo’s first custom self driving ASIC is a 5nm sensor fusion front end—not a replacement for the main Waymo Driver computer.
- The reported package measures 45 × 45 mm, contains a 208 mm² die, uses in package LPDDR5X at 273 GB/s, and consumes less than 75 watts.
- Waymo’s broader message is that autonomous driving needs tightly co designed hardware, software, and multiple sensor types—not simply a faster general purpose accelerator or a camera only stack.
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openai.comCreate a landscape editorial hero image for this Studio Global article: What did Waymo reveal at Hot Chips 2026 about its first custom self-driving processor, the 5-nanometer Sensor Fusion Processor—internally ca. Article summary: Waymo presented the Sensor Fusion Processor, reportedly called “carTPU” internally, as a purpose-built 5 nm front-end ASIC rather than a replacement for its main driving computer. Its job is to turn high-bandwidth raw se. Topic tags: general, general web. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks, charts with fake numbers, clic
Waymo’s custom Sensor Fusion Processor is best understood as the sensor-facing compute layer of the Waymo Driver. Reportedly known internally as the “carTPU,” the 5nm ASIC takes in high-bandwidth sensor streams, extracts features, and produces fused ML representations for the system’s main driving computer. It is specialized front-end silicon, not a standalone replacement for the vehicle’s full autonomy stack. 17
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The key disclosure: custom silicon before the driving “brain”
Waymo described the chip as a purpose-built 5nm ASIC engineered to process, fuse, and run neural networks on raw sensor data in real time. The company’s stated goal is to reduce the time between a sensor’s first incoming pixel and the downstream representation used for driving decisions. 17
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That division of labor matters. The ASIC handles a demanding early stage of perception, while the broader onboard platform remains heterogeneous, combining custom ML technology with CPUs, GPUs, and other accelerators for tasks such as orchestration, data movement, and logging. 1
The result is not “Waymo replaced Nvidia with one chip.” Waymo identified Nvidia and AMD among its hardware partners, alongside Micron, Samsung, SanDisk, Socionext, and TSMC. 17
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What the processor fuses in real time
Waymo’s public description explicitly names three sensor categories:
- Lidar, for three-dimensional environmental information
- Radar, for complementary detection and ranging
- Cameras, including the system’s high-resolution camera feeds
The processor performs real-time processing, feature extraction, and neural-network sensor fusion across those streams. Waymo also described temporal denoising for low-light perception. 1
Reporting on the Hot Chips presentation says the system processes 13 high-resolution camera feeds simultaneously and that camera, lidar, and radar embeddings feed the sensor-fusion encoder. 15
8 The available primary-source material does not independently confirm microphone fusion, so microphone data should not be treated as a verified feature of the disclosed processor. Waymo’s sixth-generation sensor suite does include external audio receivers, but that does not by itself prove that microphones are fused by this ASIC.
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Reported specifications from Hot Chips coverage
The most detailed figures came from Hot Chips reporting and presentation material rather than Waymo’s public announcement. Those reports describe the following configuration: 15
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| Specification | Reported detail |
|---|---|
| Process technology | TSMC 5nm N5 automotive implementation |
| Package | 45 × 45 mm FCBGA |
| Die area | 208 mm² |
| Memory | In-package LPDDR5X |
| Memory bandwidth | 273 GB/s |
| Power | Below 75 W |
| ML performance | More than 1,000 TOPS |
| Host connectivity | PCIe Gen5 x8 and 25Gb Ethernet |
The package, die, memory, and power figures should be read as reported specifications, not as details independently confirmed in Waymo’s announcement. That distinction is important because the company’s official post confirms the chip’s purpose, 5nm fabrication, heterogeneous architecture, 1,000-plus-TOPS claim, and partner ecosystem, while secondary coverage supplies much of the implementation-level detail. 17
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A heterogeneous architecture built around latency
The reported design combines Waymo-developed blocks for image processing, video codecs, MIPI sensor ingestion, and scratchpad memory with third-party GPU capability, PCIe Gen5, 25Gb Ethernet, and secure-boot IP. Coverage also reports 2 MB of banked SRAM per processing element. 15
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The architectural priority is not merely a large throughput headline. Waymo’s approach emphasizes deterministic, low-latency execution and close hardware–software co-design. Reporting from the presentation describes compiler-first execution of large “mega-kernels,” allowing the software stack and silicon to be tuned together for the path from incoming sensor data to embeddings. 15
That approach reflects the constraints of vehicle computing. The system must handle enormous data volumes in real time while operating within limits on power, heat, physical space, vibration, and fault tolerance. Waymo says its compute platform uses liquid cooling and two independent compute engines, with one able to take over if the other fails. 1
Why the 1,000-TOPS number needs context
More than 1,000 TOPS is the headline figure, but TOPS alone does not describe an autonomous-driving computer’s effectiveness. The relevant questions include which operations the number measures, how efficiently models run, how much data movement is required, and how quickly the system can move from raw sensor input to a useful representation.
Waymo’s disclosure positions the custom ASIC as a front-end accelerator optimized for the company’s own sensor suite and models. It is intended to improve bandwidth efficiency and latency by processing data near the point where they enter the vehicle, rather than sending every raw stream directly to a general-purpose central processor. 17
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The available reporting also does not establish whether the 1,000-plus-TOPS figure applies to one engine or to a redundant pair. As a result, it should not be interpreted as a simple measure of usable system throughput without further clarification. 14
The strategic message: multi-sensor autonomy and co-design
Daniel Rosenband framed Waymo’s target as a “superhuman driver with far fewer accidents than humans,” rather than a system designed merely to match human perception. That argument was presented alongside a defense of combining cameras with lidar and radar instead of relying on a camera-only approach. 6
The hardware strategy follows the same logic: Waymo is co-designing sensors, algorithms, and silicon around the requirements of autonomous driving. Its sixth-generation Driver uses a multimodal sensing system in which high-resolution cameras, imaging radar, and lidar work together. 22
Rosenband also discussed longer-term ambitions to run dramatically larger AI models in a vehicle—including an eventual trillion-parameter model—and to reduce onboard computing from a “pizza box” toward laptop size. Those are future goals, not capabilities announced as part of the current processor. 6
What Waymo actually revealed
The clearest takeaway from the disclosure is not that Waymo built a single chip capable of driving a robotaxi by itself. It is that the company is building a specialized compute pipeline around the hardest early-stage problem: converting many high-bandwidth sensor streams into reliable, low-latency representations for the main autonomy system.
The verified core of the announcement is a custom 5nm sensor-processing ASIC with more than 1,000 TOPS of ML performance, real-time fusion of camera, lidar, and radar data, a heterogeneous compute platform, redundant processing engines, and a broad hardware-partner network. 17
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The more granular Hot Chips specifications—45 × 45 mm packaging, a 208 mm² die, 273 GB/s LPDDR5X bandwidth, and sub-75-watt power—make the design more tangible, but they remain primarily reported details. 15
11 Together, the disclosures show Waymo treating autonomous driving as an edge-computing and systems-engineering problem, where latency, reliability, sensor diversity, and power efficiency matter as much as raw AI compute.
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What is the short answer to "Waymo’s 5nm CarTPU: Inside the Sensor-Fusion Processor Powering Its Robotaxis"?
Waymo’s first custom self driving ASIC is a 5nm sensor fusion front end—not a replacement for the main Waymo Driver computer.
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Waymo’s first custom self driving ASIC is a 5nm sensor fusion front end—not a replacement for the main Waymo Driver computer. The reported package measures 45 × 45 mm, contains a 208 mm² die, uses in package LPDDR5X at 273 GB/s, and consumes less than 75 watts.
What should I do next in practice?
Waymo’s broader message is that autonomous driving needs tightly co designed hardware, software, and multiple sensor types—not simply a faster general purpose accelerator or a camera only stack.