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WAIC 2026 signals China’s shift from single-chip performance to AI systems
The clearest signal from WAIC 2026 was that Chinese AI hardware companies are increasingly defining their products as supernodes and complete computing systems—not simply as individual chips. Biren Technology introduced an NPO optical supernode supporting up to 1,024 cards, with BLink 2.0 focused on memory semantic...
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Key takeaways
- The clearest signal from WAIC 2026 was that Chinese AI hardware companies are increasingly defining their products as supernodes and complete computing systems—not simply as individual chips.
- Biren Technology introduced an NPO optical supernode supporting up to 1,024 cards, with BLink 2.0 focused on memory semantic interconnects, in network computing, congestion control and link repair.
- Kunlunxin emphasized dense 32 and 64 card racks and production delivery. By contrast, the available public evidence is not detailed or reliable enough to confirm the specific supernode architectures, memory models or...
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openai.comCreate a landscape editorial hero image for this Studio Global article: What did WAIC 2026 in Shanghai reveal about China’s shift from competing primarily on single-chip performance to competing on supernode-scal. Article summary: WAIC 2026 signaled a credible shift in China’s AI-compute competition: vendors were no longer presenting accelerators mainly as standalone peak-FLOPS products, but as parts of rack- to cluster-scale systems in which inte. Topic tags: general, general web, news, user generated, documentation. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, water
The most important message from WAIC 2026 in Shanghai was not simply which company claimed the highest chip-level compute figure. It was that AI infrastructure competition is moving up the stack—from accelerators to supernodes and complete rack-scale systems.
Exhibitors increasingly presented not only processors, but also Scale-up interconnects, memory access models, rack density, liquid cooling, network reliability and software stacks. The goal of a supernode is to make dozens, hundreds or even thousands of accelerators behave more like one coordinated computer than a collection of separate servers.7
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Still, calling WAIC 2026 the definitive moment when Chinese vendors “shifted from chips to systems” is an interpretation based on exhibits and company announcements, not an industry fact established by independent testing.
Why supernodes matter more than peak chip specifications
Large-model training and inference require accelerators to exchange parameters, activations, gradients and routing data repeatedly. If bandwidth is insufficient, latency is too high or the network becomes congested, expensive processors sit idle. Theoretical FLOPS then fail to translate into useful throughput.
A supernode therefore attempts to solve several problems at once:
- increase bandwidth and reduce latency between accelerators;
- make collective communication more predictable while managing congestion and failures;
- expand the memory space available to a model;
- improve sustained operation through rack, power and cooling design; and
- give compilers, runtimes and schedulers a way to manage larger pools of heterogeneous resources.
That changes the metrics customers care about. Buyers ultimately want completed training runs or sustained inference tokens—not an isolated peak-FLOPS number. Accelerator utilization, communication overhead, power consumption, cooling, reliability, software migration costs and operational complexity all affect the real cost per usable token.
Biren Technology: expanding the physical Scale-up domain with NPO and BLink 2.0
Biren Technology unveiled a supernode architecture at WAIC 2026 based on near-package optics, or NPO, and a distributed, decoupled design. The company says a single supernode can support Scale-up expansion to as many as 1,024 cards.1
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NPO places optical interconnect engines closer to the compute package, shortening the connection path. Fiber then links physically separated compute and networking nodes. The design is presented as a response to the distance, power and signal-integrity limits that conventional electrical connections face when systems scale.4
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Biren positions BLink 2.0 as a supernode interconnect protocol rather than merely a link technology. The company has highlighted four capabilities:
- Memory-semantic interconnect: the stated goal is to let up to 1,024 GPUs share a single memory space;
- In-network computing: moving some communication-related mathematical operations into network equipment;
- Congestion control: reducing bottlenecks during large-scale communication; and
- Link repair: providing layers of fault protection from the physical layer through the software framework.
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The announcement shows that Biren’s focus has expanded from the performance of one card to the question of how a large number of cards can work together. But shared memory, reliability and effective throughput remain vendor-stated architectural goals in the available material. They should not be treated as independently validated results across multiple workloads.
Yixin Intelligent: a RISC-V and electrical-interconnect system strategy
Yixin Intelligent presented what it described as the industry’s first RISC-V AI supernode. The system is built around the company’s Epoch cloud AI accelerator and combines ELink high-speed interconnect, an orthogonal backplane-free structure, liquid cooling and a full software stack.19
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Epoch uses the open RISC-V instruction set and supports block-quantized FP8. Yixin said its next-generation products are planned to add lower-precision formats including EXFP4 and MXFP4, while also increasing compute capacity, memory capacity and memory bandwidth.22
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Lower-precision formats can improve compute and memory efficiency for suitable training or inference workloads. The actual benefit, however, depends on the model, operators and software implementation; the name of a precision format alone does not establish a uniform performance gain.
Yixin also emphasizes an orthogonal, backplane-free design. Public material attributed to the company says the approach can cut interconnect hardware costs by 80% and bring latency into the hundreds-of-nanoseconds range.13
31 Those figures should be understood as vendor-stated design targets, not independently established benchmarks across different system sizes and workloads.
The contrast with Biren is instructive. Biren’s public strategy centers on optical interconnect and a very large unified memory-semantic domain. Yixin’s presentation emphasizes an integrated path from open instruction-set architecture and accelerator design to precision support, interconnect, liquid cooling and software. Both are selling system-level capability, but their technical priorities differ.
Kunlunxin: dense racks and the ability to deliver
Kunlunxin, Baidu’s AI-chip unit, was reported to have shown supernode products integrating 32 or 64 accelerator cards, using a proprietary ultra-high-density architecture. Related material says the design can scale to 512 cards.7
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This approach does not initially rely on an optics-first message. Instead, it focuses on fitting dozens of accelerators into a rack that can be deployed and delivered as a production system. Media reports have described the 32- and 64-card products as among China’s early domestically developed supernodes to reach mass production and delivery.11
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That highlights another dimension of the supernode race. The ability to connect more chips does not automatically mean customers can operate them at scale. Rack density, power delivery, cooling, manufacturing consistency, software compatibility and delivery capacity all determine whether a design moves from a trade-show floor into a data centre.
What the evidence does—and does not—show about other vendors
The supplied material also mentions Infinigence CoreX, SingularMOL and Infinigence, along with different system concepts involving training-oriented silicon, a third-generation architecture, chiplet interconnect and virtual-supercluster software.
However, the available sources do not provide enough specific, reliable and independently cross-checkable information to confirm these companies’ supernode topologies, memory-coherence or sharing limits, interconnect types, bandwidth, precision support or actual delivery status.
The more cautious conclusions are therefore:
- there is insufficient evidence to establish the specific optical or electrical interconnect and system scale of Infinigence CoreX;
- there is insufficient evidence to verify a detailed chiplet-supernode structure, memory model or bandwidth figure for SingularMOL; and
- the available material does not establish the compatibility range or performance of Infinigence’s proposed virtual-supercluster software, including whether it can uniformly schedule accelerators across vendors.
Concept demonstrations, secondary reports or descriptions without technical detail should not be rewritten as proof that a product is already in volume production, offers unified memory or delivers a particular performance level.
Software orchestration could become the decisive layer
As customers combine domestic accelerators from different suppliers to manage availability, cost and risk, the software layer becomes more important. Compilers, operator libraries, communication libraries, runtimes, cluster schedulers, monitoring systems and fault-management tools must hide as much of the hardware variation as possible.
That is why a usable supernode means more than placing more cards in one rack. Operators also need answers to practical questions: Can a model be partitioned efficiently? Can communication be scheduled? Will one failure interrupt the job? Can resources be monitored? How much code must developers rewrite for each accelerator architecture?
Physical supernodes and software-defined resource pools are complementary. The former makes accelerators within one hardware domain work more closely together. The latter can make different clusters and accelerator types easier to use as a unified operational resource. But the available sources are not sufficient to make firm claims about the compatibility range or performance of specific platforms such as Infinigence’s.
The real takeaway from WAIC 2026
WAIC 2026 did not prove that Chinese AI systems have universally matched leading global platforms in performance, software maturity or ecosystem depth. It did show that the basis for competition is changing.
Peak single-chip performance still matters, but it is no longer enough to describe the capability of a large-model system. Biren’s 1,024-card NPO architecture, BLink 2.0 and unified memory-semantic goals represent an optical approach to expanding the Scale-up domain. Yixin’s Epoch, RISC-V and ELink platform represent an integrated accelerator-and-system approach. Kunlunxin puts greater emphasis on dense rack integration and delivery maturity.4
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The more accurate conclusion is not that Chinese vendors definitively ended single-chip competition at WAIC 2026. It is that they are increasingly defining the product as a complete system: accelerator, interconnect, memory, cooling, networking and software working together.
For buyers, the next comparison will therefore be less about the theoretical compute printed on a specification sheet and more about effective throughput, availability, scaling cost, energy and cooling requirements, and the difficulty of moving software between platforms.
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The clearest signal from WAIC 2026 was that Chinese AI hardware companies are increasingly defining their products as supernodes and complete computing systems—not simply as individual chips.
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The clearest signal from WAIC 2026 was that Chinese AI hardware companies are increasingly defining their products as supernodes and complete computing systems—not simply as individual chips. Biren Technology introduced an NPO optical supernode supporting up to 1,024 cards, with BLink 2.0 focused on memory semantic interconnects, in network computing, congestion control and link repair.
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Kunlunxin emphasized dense 32 and 64 card racks and production delivery. By contrast, the available public evidence is not detailed or reliable enough to confirm the specific supernode architectures, memory models or...