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TSMC’s AI Strategy: 50× More System Compute by 2029 Through Packaging and Photonics
TSMC says SoIC 3D stacking and CoWoS advanced packaging could raise system computing performance to about 50 times its 2024 level by 2029. April Li argued that the next phase of AI will be built by integrating compute, memory, interconnects, storage and power management across chips, servers and data centers.
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Key takeaways
- TSMC says SoIC 3D stacking and CoWoS advanced packaging could raise system computing performance to about 50 times its 2024 level by 2029.
- April Li argued that the next phase of AI will be built by integrating compute, memory, interconnects, storage and power management across chips, servers and data centers.
- Inference is becoming the key demand driver: TSMC cited roughly fivefold annual AI computing growth and nearly 500 fold growth in inference token volume since 2022.
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openai.comCreate a landscape editorial hero image for this Studio Global article: What did TSMC announce at SEMICON Taiwan 2026 about its strategy for the “true industrialization of AI,” including its projection of a 50-fo. Article summary: TSMC’s message was that AI is becoming a systems-integration business, not merely a race to make faster chips or models. Its strategy combines leading-edge logic with 3DFabric packaging and silicon photonics to address t. Topic tags: general, general web, user generated, government, news. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermar
TSMC’s central message at SEMICON Taiwan 2026 was that the next phase of AI will be won at the system level, not by improving processors or models in isolation. The company’s roadmap combines advanced logic, SoIC 3D stacking, CoWoS 2.5D packaging and silicon photonics to move data more efficiently through increasingly large AI systems. 1
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The headline: 50× more system compute by 2029
TSMC projects that integrating SoIC and CoWoS could increase overall system computing performance to approximately 50 times its 2024 level by 2029. The projection reflects a shift away from treating the processor as the main unit of progress and toward combining multiple compute dies, high-bandwidth memory and high-density interconnects in one system. 3
The reported 3DFabric roadmap includes N2P-on-N3P SoIC integration in 2026 and A14-on-A14 integration in 2029, with the interconnect pitch reaching 4.5 microns. These milestones are intended to increase the density and efficiency of connections between stacked and adjacent components. 3
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Why inference is changing AI infrastructure
April Li, TSMC’s AI and high-performance-computing business development director, said AI-computing demand is growing at roughly five times per year. She also cited an almost 500-fold increase in inference-token volume from 2022. 1
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That growth is increasingly coming from inference—the stage when AI systems respond to users or perform tasks—rather than only from training larger models. Reasoning systems and agentic AI can generate and process substantially more tokens per interaction, while enterprise agents and physical-AI applications are designed to run continuously in real-world workflows. 1
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The implication is important: future infrastructure must be designed for sustained, high-volume inference. More users, more frequent queries and more computation per query all increase pressure on accelerators, memory, networking and power systems.
TSMC’s argument: the bottleneck is data movement
Li’s case for system-level co-design rests on an efficiency problem. Data movement can account for as much as 60% of activity in typical AI workloads, while expensive AI accelerators may operate at less than 40% utilization. 1
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That means adding more compute alone may not deliver proportional gains. The system also has to move data between logic and memory, across packages, through server racks and across the data center without exhausting power or cooling capacity.
TSMC’s proposed answer is to optimize the entire path—from compute and memory to interconnects, storage, power delivery, cooling, racks and data-center infrastructure. In this model, advanced packaging is not simply a manufacturing step; it is part of the architecture of the AI system.
Bigger CoWoS packages for multi-die AI systems
TSMC is already producing 5.5-reticle CoWoS packages, according to reporting on its advanced-packaging roadmap. It plans to move toward 14-reticle packages around 2028, with reported configurations of roughly 10 compute dies and 20 HBM stacks. 3
CoWoS, or chip-on-wafer-on-substrate, places logic and high-bandwidth memory in a tightly integrated package. Larger package footprints allow AI accelerators to combine more compute and memory without relying on a single enormous monolithic die.
This approach also reflects the practical limits of advanced chip manufacturing. Splitting a system across multiple dies can improve manufacturing flexibility, but it makes package design, interconnect density, testing and thermal management more important.
Silicon photonics is the next layer
TSMC also positioned silicon photonics and co-packaged optics as a way to address the limits of electrical connections inside AI infrastructure. Its COUPE platform is reported to have a bandwidth roadmap rising from 3.2 Tbps to more than 12.8 Tbps. TSMC has also forecast that silicon photonics could account for more than half of the optical-transceiver market by 2027, while some suppliers are expected to begin volume production of co-packaged optics in late 2026. 3
The broader goal is to bring optical interconnects closer to the compute package. Shorter distances between electronic and photonic components can support higher bandwidth and better power efficiency, although the approach introduces additional requirements for lasers, fiber connectors, packaging and validation. 10
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Capacity is still the unresolved constraint
The roadmap does not eliminate the supply problem. Industry estimates put TSMC’s CoWoS capacity at roughly 120,000 to 140,000 wafers per month by late 2026, up from approximately 13,000 to 16,000 per month in late 2023. Those figures are market estimates rather than a capacity number formally disclosed in the SEMICON Taiwan event coverage. 6
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Institutional-investor reporting has estimated that the CoWoS supply-demand gap could narrow from about 20% to roughly 10% by the end of 2026 as capacity expands. That would represent an improvement, but it would still mean demand exceeds available supply. 36
Allocation is another risk. Nvidia has been reported to account for roughly 60% of TSMC’s 2026 CoWoS demand or output, leaving AMD, Broadcom and hyperscalers competing for the remaining capacity. This is market analysis, not a new allocation figure announced by TSMC at SEMICON Taiwan. 4
TSMC’s expanding role in the AI stack
The strategic change is broader than a packaging upgrade. Li described TSMC’s role as extending from the silicon to the data center and ultimately to the token generated by the AI system. 1
That ambition would make TSMC an increasingly important coordinator of the physical AI stack: leading-edge logic, HBM integration, advanced packaging, optical I/O, thermal design, power delivery and system validation. The remaining challenges therefore include not only wafer and package output, but also optical components, testing, cooling and coordination across suppliers.
TSMC’s “true industrialization of AI” thesis is consequently a bet on integration. Its 50× performance projection is ambitious, but the company’s own roadmap makes clear that achieving it depends on solving the connections between components—and scaling the supply chain that builds them—as much as on producing faster chips.
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What is the short answer to "TSMC’s AI Strategy: 50× More System Compute by 2029 Through Packaging and Photonics"?
TSMC says SoIC 3D stacking and CoWoS advanced packaging could raise system computing performance to about 50 times its 2024 level by 2029.
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TSMC says SoIC 3D stacking and CoWoS advanced packaging could raise system computing performance to about 50 times its 2024 level by 2029. April Li argued that the next phase of AI will be built by integrating compute, memory, interconnects, storage and power management across chips, servers and data centers.
What should I do next in practice?
Inference is becoming the key demand driver: TSMC cited roughly fivefold annual AI computing growth and nearly 500 fold growth in inference token volume since 2022.