How the Kirin 9050 Pro’s two-die LogicFolding design works

The Kirin 9050 Pro’s headline design choice is to stack two active silicon dies instead of relying only on smaller transistors. Geekerwan’s teardown and die images attributed to Kurnal Insights show a compute-focused layer bonded to a layer centered on SRAM and cache. The approach can increase effective chip density and shorten some connections, but the reported figures do not establish that the chip uses leading-edge transistor scaling.31113

What the teardowns show

The two dies appear to be similarly sized: about 11.13 × 10.84 mm, or 120.65 mm² each. Reports describe one die as focused on computing logic and the other as carrying SRAM and cache, along with functions such as I/O and clock circuitry.111315

The layers are joined face-to-face using copper-to-copper hybrid bonding. The reported bonding pitch is about 1.5 micrometers, enabling closely spaced vertical links between the dies.1315

Reports also cite roughly 50 million vertical interconnects and about 80,000 through-silicon vias (TSVs). These are different interconnect categories, so the counts should not be added together or treated as equivalent. Available descriptions also vary on the TSVs’ routing; the figures are best read as separate reported counts, not a single verified map of every connection.13515

Process estimates and the density claim

Teardown coverage infers that the compute die uses SMIC’s N+3 process and the SRAM-oriented die uses N+2. These are reported estimates, not definitive confirmation of the manufacturing process for each layer.1115

Huawei reports effective density of about 238 million transistors per square millimeter, compared with roughly 155 million for the baseline it cites—an increase of about 54%. That figure describes the reported density benefit of the stacked design; it does not mean either die independently gained that much transistor density through a smaller process node.1211

What the power and benchmark reports say

Huawei claims that, at matched performance, power consumption falls 41% for the CPU, 58% for the GPU and 66% for the NPU. These are company figures, not measurements established by the teardown itself; coverage of the launch noted that the claims had not been independently audited.1248

Benchmark reporting is more qualified than a simple claim of flagship parity. Bernstein research was reported to find the Kirin 9050 Pro ahead of Apple’s A17 Pro on some Geekbench 6 multi-core tests, while still behind Apple’s newer A20 Pro in its comparison. That points to progress in selected workloads, not a general win across chips or benchmarks.49

The processor is reported in higher-end Mate 90 models, making LogicFolding a commercial design rather than only a proposed architecture.6

The benefits—and the limits—under export controls

Stacking gives Huawei another way to increase effective density without depending entirely on conventional process-node scaling. Separating compute and memory functions may also put different parts of the design on different processes and bring some data paths closer together.711

The trade-off is added integration complexity: two active dies must be manufactured and joined with fine-pitch bonding. The available reports do not establish production yields, costs or thermal performance, so those practical outcomes remain uncertain. And stacking does not make a transistor fabricated on an older process equivalent to one made on a leading-edge node.

In the context of U.S. export controls, LogicFolding is best understood as a way to work around some scaling constraints—not as proof of process-node parity or a fully independent supply chain. Reporting on the chip says its supply chain remains undisclosed.19