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Lanxin’s LX500 Supernode Pushes RISC-V AI From Chip to Cluster
Lanxin announced its converged computing supernode at the October 19, 2026 RISC V China Summit. The reported LX500 configuration includes 75 TOPS INT8 AI compute, 32 performance cores and 16 efficiency cores; these are stated specifications, not proof of cluster scale performance.[1][2]
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Key takeaways
- Lanxin announced its converged computing supernode at the October 19, 2026 RISC V China Summit.
- The reported LX500 configuration includes 75 TOPS INT8 AI compute, 32 performance cores and 16 efficiency cores; these are stated specifications, not proof of cluster scale performance.[1][2]
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Lanxin Computing announced its “converged-computing supernode” at the 2026 RISC-V China Summit on October 19. The launch extends the company’s LX500-based approach from a chip and server toward clustered AI infrastructure. CTO Jia Xinxia’s keynote, “LX500: Unlocking a New Path for AI Inference,” presented the company’s RISC-V and AI integration work and productization progress.1
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The central idea is to bring general-purpose computing and AI computation together on one chip, with unified memory shared between the compute units. That design aims to reduce data movement compared with systems that separate CPUs and AI accelerators and move data between memory spaces over links such as PCIe.2
What Lanxin reports about the LX500
Lanxin’s reported LX500 specifications include:
- 48 RISC-V CPU cores: 32 performance cores and 16 efficiency cores.
- AI engines: AI vector and matrix engines rated at 75 TOPS for INT8, with support reported from INT4 through FP32.
- Memory: A unified-memory design sharing DDR5 resources between CPU and AI compute, with CXL expansion also reported.
- RISC-V compatibility: RVA23 and RVV 1.0 support are reported in coverage of the chip.
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These figures describe reported product specifications, not independent benchmark results. One report gives additional memory details, including CXL 2.0 expansion and up to 2TB of addressability; those figures have not been established by the summit coverage itself.6
Why unified memory could matter for inference
In a conventional CPU-plus-accelerator arrangement, data may need to move between separate memory spaces. Lanxin’s approach is intended to reduce that movement by putting CPU and AI compute on the same chip and sharing memory resources.2
That could reduce the time and system traffic associated with transferring data during inference. The summit coverage says the design targets first-token latency, prompt prefill and long-context workloads. It does not provide quantified results showing how much those measures improve, however, so the architecture’s intended benefit should not be confused with a demonstrated performance gain.2
The supernode’s scale is still an open question
The announcement marks an expansion from an individual chip and server toward cluster-level infrastructure.1
2 But the available reports do not specify the supernode’s chip count or interconnect design. Without those details, it is not possible to assess its aggregate compute, memory topology or scaling performance.
The sources describe earlier LX500-related milestones, including the chip’s February 2026 power-on and Lenovo’s LX500-powered WR5219 G5 server being shown in July.1
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14 Those steps provide product context, but they do not establish how the new supernode performs under real workloads.
A product milestone, not yet a performance verdict
Lanxin’s announcement illustrates one route for extending RISC-V from processors into servers and AI infrastructure. The practical test is whether the hardware, software ecosystem and system-level design can support reliable, competitive deployments. Industry coverage has likewise identified adoption in demanding telecom, finance and government environments as a test for RISC-V server platforms.5
For now, the LX500’s reported specifications and unified-memory approach make the supernode a notable product announcement. A fuller assessment will require disclosed cluster details, workload-level benchmarks and evidence from sustained deployments.
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Lanxin announced its converged computing supernode at the October 19, 2026 RISC V China Summit.
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Lanxin announced its converged computing supernode at the October 19, 2026 RISC V China Summit. The reported LX500 configuration includes 75 TOPS INT8 AI compute, 32 performance cores and 16 efficiency cores; these are stated specifications, not proof of cluster scale performance.[1][2]