Samsung’s CUBE strategy is an attempt to address the AI industry’s memory bottleneck by treating memory as a three-dimensional system rather than a collection of chips laid out across a two-dimensional package. Announced at the Memory Executive Summit during SEMICON Taiwan 2026, CUBE stands for Capacity, Utilization, Bandwidth and Efficiency. 24

The strategy combines a conventional next-generation HBM product—HBM5—with more speculative architectures that place memory and logic closer together. The important distinction is that Samsung has announced development targets and concepts, not a complete set of shipping specifications.

What Samsung’s four CUBE priorities mean

Capacity: expand upward instead of outward

Samsung’s stated approach is to increase memory capacity vertically without expanding the printed-circuit-board footprint. That matters for AI systems, where accelerators need access to larger pools of memory but board area, package size and power delivery are constrained. 249

Utilization: make every layer do more useful work

CUBE’s utilization pillar goes beyond simply adding more stacked memory dies. Samsung describes optimizing the placement and relationship between logic and memory so that data does not have to travel unnecessarily or wait on inefficient paths. 449

Bandwidth: replace long horizontal paths with vertical links

The roadmap aims to improve bandwidth by shortening the distance between processing logic and memory. In the zHBM concept, that means using dense vertical connections rather than relying on the conventional arrangement in which HBM sits next to the accelerator. 812

Efficiency: reduce the cost of moving data

Samsung’s efficiency goal covers both power and heat. Moving data consumes energy, and denser AI packages generate more heat; the CUBE approach therefore treats bandwidth, power consumption and thermal resistance as linked design problems rather than separate specifications. 551

HBM5: ambitious targets, limited detail

Samsung is developing HBM5 as the next generation after HBM4E. Its stated targets are:

• 2× the performance of HBM4E
• 20% higher performance per watt
• 20% lower thermal resistance 126

Reporting also describes a planned 1c-class DRAM process, an in-house 2nm base die, and a Heat Path Block intended to improve heat removal from the stack. 37

Those numbers should be read as targets rather than independently demonstrated product results. Samsung has not published an absolute HBM5 bandwidth figure, a final capacity, a confirmed stack height or enough detail to define precisely what “twice the performance” measures. It could refer to an interface metric, per-stack throughput, or a broader system-level capability; the available disclosure does not resolve that question. 7

That ambiguity makes it impossible to convert the 2× claim into a reliable HBM5 figure in terabytes per second. A comparison with any existing HBM4E demonstration would require the same definition of performance, the same stack configuration and equivalent test conditions.

zHBM moves memory directly onto the accelerator

The more radical part of the roadmap is zHBM. Conventional HBM is positioned alongside an AI accelerator, typically connected through an advanced package or interposer. zHBM would instead place the memory directly above the CPU, GPU or other accelerator, creating a vertical memory-and-logic structure. 81217

Samsung’s proposed implementation uses wafer-level integration and hybrid copper bonding. Direct copper-to-copper connections can provide shorter, denser signal paths than a conventional arrangement, which is intended to increase bandwidth while reducing the energy required to move data. 17

Samsung has published a headline target of up to 8× the performance of a reference HBM design and up to 3× the performance per watt, alongside a large reduction in thermal resistance. 1618

Why zHBM is sometimes described as 4× and sometimes 8×

The numbers circulating around zHBM are not always directly comparable. Samsung’s clearest public formulation describes a next-generation interface system incorporating zHBM as reaching approximately 8× the performance of HBM5. 1822 Other reporting compares the concept with HBM4E or presents a 4–8× range. 11352

The discrepancy may reflect different reference generations, different definitions of “performance,” or a distinction between interface performance and the performance of a complete memory stack. Samsung has not disclosed enough absolute metrics to reconcile those comparisons. The safe conclusion is that zHBM is a proposal for a substantially denser and shorter memory interface—not a verified 4× or 8× gain in a shipping AI system.

zHBM commercialization remains uncertain

Samsung has presented zHBM as a concept architecture and has not provided a firm production timetable in the supplied reporting. Claims that it will reach commercialization in a specific year should therefore be treated as industry expectations rather than Samsung-confirmed guidance. 1323

That distinction is important because the architecture introduces manufacturing and packaging problems that do not appear in a headline multiplier.

zNAND-O targets a different AI-memory problem

Samsung’s zNAND-O is separate from server-oriented HBM. It is designed as a vertically integrated NAND-based solution for on-device AI and other applications that need high storage density with faster access than conventional NAND can provide. Reporting describes a goal of substantially higher bit density than DRAM, together with improved read bandwidth and power efficiency relative to ordinary NAND. 4613

Some reports put customer sampling at 2028, but the supplied coverage is not consistent about the status of that timetable. It is best treated as a reported plan rather than a guaranteed launch date. 131416

Samsung’s market position does not settle the HBM race

Samsung entered the roadmap announcement from a position of strength in the broader DRAM market. Counterpoint Research data put Samsung at 39% of global DRAM revenue in Q2 2026, ahead of SK hynix at 26% and Micron at 25%. 33

That statistic should not be confused with leadership in every HBM generation or in 3D memory packaging. Overall DRAM revenue includes markets beyond advanced AI accelerators, so it does not prove that Samsung has already established a lead in HBM5, zHBM or hybrid-bonded memory.

The competitive question is therefore less about who currently sells the most DRAM and more about which company can turn a promising architecture into reliable, high-volume packages that customers can integrate into AI systems.

The engineering issues that will decide CUBE’s outcome

Thermal management

Putting memory directly above a powerful accelerator shortens the electrical path, but it can also place memory in a more difficult thermal environment. The relevant tests will include sustained temperatures, thermal gradients, hotspot control, cooling compatibility and reliability under real AI workloads—not just a headline reduction in thermal resistance.

Hybrid-bonding yield

zHBM depends on extremely accurate wafer alignment and clean, flat bonding surfaces. Defects become more consequential as the bonded area and connection density increase. Manufacturers will need effective known-good-die screening, process control and methods for handling defective or partially defective assemblies.

Testing and long-term reliability

A vertical package must be tested after bonding, and manufacturers must identify latent interconnect defects while controlling warpage, mechanical stress, electromigration and the effects of repeated thermal cycling. These requirements can affect both yield and cost.

Stack height and package integration

Adding layers can increase capacity, but it can also make cooling, power delivery and mechanical reliability more difficult. The optimal design will depend on the accelerator’s power level, the customer’s package and cooling system, required capacity, and the wider manufacturing ecosystem.

Bottom line

CUBE is Samsung’s attempt to compete in AI memory through vertical integration rather than through faster DRAM alone. HBM5 is the nearer-term product direction, with targets of 2× HBM4E performance, 20% better performance per watt and 20% lower thermal resistance. zHBM is the longer-term architectural bet: put memory directly above the accelerator and use hybrid copper bonding to shorten the data path.

The roadmap is technically significant, but its largest numbers remain targets with incomplete definitions. Samsung’s eventual position will depend less on whether a presentation can claim 2× or 8× performance than on whether the company can deliver the required thermal behavior, bonding yield, test coverage, reliability and customer-level package integration.

Samsung’s CUBE strategy is an attempt to address the AI industry’s memory bottleneck by treating memory as a three-dimensional system rather than a collection of chips laid out across a two-dimensional package. Announced at the Memory Executive Summit during SEMICON Taiwan 2026, CUBE stands for Capacity, Utilization, Bandwidth and Efficiency. 24

The strategy combines a conventional next-generation HBM product—HBM5—with more speculative architectures that place memory and logic closer together. The important distinction is that Samsung has announced development targets and concepts, not a complete set of shipping specifications.

What Samsung’s four CUBE priorities mean

Capacity: expand upward instead of outward

Samsung’s stated approach is to increase memory capacity vertically without expanding the printed-circuit-board footprint. That matters for AI systems, where accelerators need access to larger pools of memory but board area, package size and power delivery are constrained. 249

Utilization: make every layer do more useful work

CUBE’s utilization pillar goes beyond simply adding more stacked memory dies. Samsung describes optimizing the placement and relationship between logic and memory so that data does not have to travel unnecessarily or wait on inefficient paths. 449

Bandwidth: replace long horizontal paths with vertical links

The roadmap aims to improve bandwidth by shortening the distance between processing logic and memory. In the zHBM concept, that means using dense vertical connections rather than relying on the conventional arrangement in which HBM sits next to the accelerator. 812

Efficiency: reduce the cost of moving data

Samsung’s efficiency goal covers both power and heat. Moving data consumes energy, and denser AI packages generate more heat; the CUBE approach therefore treats bandwidth, power consumption and thermal resistance as linked design problems rather than separate specifications. 551

HBM5: ambitious targets, limited detail

Samsung is developing HBM5 as the next generation after HBM4E. Its stated targets are:

• 2× the performance of HBM4E
• 20% higher performance per watt
• 20% lower thermal resistance 126

Reporting also describes a planned 1c-class DRAM process, an in-house 2nm base die, and a Heat Path Block intended to improve heat removal from the stack. 37

Those numbers should be read as targets rather than independently demonstrated product results. Samsung has not published an absolute HBM5 bandwidth figure, a final capacity, a confirmed stack height or enough detail to define precisely what “twice the performance” measures. It could refer to an interface metric, per-stack throughput, or a broader system-level capability; the available disclosure does not resolve that question. 7

That ambiguity makes it impossible to convert the 2× claim into a reliable HBM5 figure in terabytes per second. A comparison with any existing HBM4E demonstration would require the same definition of performance, the same stack configuration and equivalent test conditions.

zHBM moves memory directly onto the accelerator

The more radical part of the roadmap is zHBM. Conventional HBM is positioned alongside an AI accelerator, typically connected through an advanced package or interposer. zHBM would instead place the memory directly above the CPU, GPU or other accelerator, creating a vertical memory-and-logic structure. 81217

Samsung’s proposed implementation uses wafer-level integration and hybrid copper bonding. Direct copper-to-copper connections can provide shorter, denser signal paths than a conventional arrangement, which is intended to increase bandwidth while reducing the energy required to move data. 17

Samsung has published a headline target of up to 8× the performance of a reference HBM design and up to 3× the performance per watt, alongside a large reduction in thermal resistance. 1618

Why zHBM is sometimes described as 4× and sometimes 8×

The numbers circulating around zHBM are not always directly comparable. Samsung’s clearest public formulation describes a next-generation interface system incorporating zHBM as reaching approximately 8× the performance of HBM5. 1822 Other reporting compares the concept with HBM4E or presents a 4–8× range. 11352

The discrepancy may reflect different reference generations, different definitions of “performance,” or a distinction between interface performance and the performance of a complete memory stack. Samsung has not disclosed enough absolute metrics to reconcile those comparisons. The safe conclusion is that zHBM is a proposal for a substantially denser and shorter memory interface—not a verified 4× or 8× gain in a shipping AI system.

zHBM commercialization remains uncertain

Samsung has presented zHBM as a concept architecture and has not provided a firm production timetable in the supplied reporting. Claims that it will reach commercialization in a specific year should therefore be treated as industry expectations rather than Samsung-confirmed guidance. 1323

That distinction is important because the architecture introduces manufacturing and packaging problems that do not appear in a headline multiplier.

zNAND-O targets a different AI-memory problem

Samsung’s zNAND-O is separate from server-oriented HBM. It is designed as a vertically integrated NAND-based solution for on-device AI and other applications that need high storage density with faster access than conventional NAND can provide. Reporting describes a goal of substantially higher bit density than DRAM, together with improved read bandwidth and power efficiency relative to ordinary NAND. 4613

Some reports put customer sampling at 2028, but the supplied coverage is not consistent about the status of that timetable. It is best treated as a reported plan rather than a guaranteed launch date. 131416

Samsung’s market position does not settle the HBM race

Samsung entered the roadmap announcement from a position of strength in the broader DRAM market. Counterpoint Research data put Samsung at 39% of global DRAM revenue in Q2 2026, ahead of SK hynix at 26% and Micron at 25%. 33

That statistic should not be confused with leadership in every HBM generation or in 3D memory packaging. Overall DRAM revenue includes markets beyond advanced AI accelerators, so it does not prove that Samsung has already established a lead in HBM5, zHBM or hybrid-bonded memory.

The competitive question is therefore less about who currently sells the most DRAM and more about which company can turn a promising architecture into reliable, high-volume packages that customers can integrate into AI systems.

The engineering issues that will decide CUBE’s outcome

Thermal management

Putting memory directly above a powerful accelerator shortens the electrical path, but it can also place memory in a more difficult thermal environment. The relevant tests will include sustained temperatures, thermal gradients, hotspot control, cooling compatibility and reliability under real AI workloads—not just a headline reduction in thermal resistance.

Hybrid-bonding yield

zHBM depends on extremely accurate wafer alignment and clean, flat bonding surfaces. Defects become more consequential as the bonded area and connection density increase. Manufacturers will need effective known-good-die screening, process control and methods for handling defective or partially defective assemblies.

Testing and long-term reliability

A vertical package must be tested after bonding, and manufacturers must identify latent interconnect defects while controlling warpage, mechanical stress, electromigration and the effects of repeated thermal cycling. These requirements can affect both yield and cost.

Stack height and package integration

Adding layers can increase capacity, but it can also make cooling, power delivery and mechanical reliability more difficult. The optimal design will depend on the accelerator’s power level, the customer’s package and cooling system, required capacity, and the wider manufacturing ecosystem.

Bottom line

CUBE is Samsung’s attempt to compete in AI memory through vertical integration rather than through faster DRAM alone. HBM5 is the nearer-term product direction, with targets of 2× HBM4E performance, 20% better performance per watt and 20% lower thermal resistance. zHBM is the longer-term architectural bet: put memory directly above the accelerator and use hybrid copper bonding to shorten the data path.

The roadmap is technically significant, but its largest numbers remain targets with incomplete definitions. Samsung’s eventual position will depend less on whether a presentation can claim 2× or 8× performance than on whether the company can deliver the required thermal behavior, bonding yield, test coverage, reliability and customer-level package integration.