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Samsung and SK hynix’s HBM4E Roadmaps Show Why AI Memory Is Becoming a Packaging Race
Samsung’s 12 layer HBM4E samples began shipping to major customers in late May at a stable 14 Gbps per pin, delivering 3.6 TB/s and 48 GB per stack; its planned 16 Gbps version targets roughly 4 TB/s, but these remain... Samsung’s long term direction is custom cHBM followed by zHBM, which would vertically integrate...
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Key takeaways
- Samsung’s 12 layer HBM4E samples began shipping to major customers in late May at a stable 14 Gbps per pin, delivering 3.6 TB/s and 48 GB per stack; its planned 16 Gbps version targets roughly 4 TB/s, but these remain...
- Samsung’s long term direction is custom cHBM followed by zHBM, which would vertically integrate processor logic and memory; SK hynix is concentrating on package level cooling, warpage, stack height, and interconnect c...
- SK hynix is researching hybrid bonding for stacks beyond 16 layers, but says it is unlikely to be ready for HBM4E and could arrive with HBM5 at the earliest.
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openai.comCreate a landscape editorial hero image for this Studio Global article: What did Samsung and SK hynix reveal at Hot Chips 2026 about their HBM roadmaps, including Samsung’s planned 16 Gbps-per-pin HBM4E reaching. Article summary: Samsung presented a roadmap centered on faster HBM4E, increasingly customized base dies, and ultimately processor-on-memory zHBM; SK hynix emphasized that advanced packaging, thermals, wafer warpage, and stack-height lim. Topic tags: general, general web, user generated, news. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks, charts wi
Samsung and SK hynix used Hot Chips 2026 to present two different answers to the same AI-memory problem: how to deliver more bandwidth without letting heat, package size, and manufacturing complexity overwhelm the design. Samsung emphasized speed, customer-specific base dies, and a future in which memory sits directly on the processor. SK hynix focused more heavily on the package itself—cooling, warpage, interconnects, and the physical limits of taller stacks. 2
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The headline figures are ambitious, but they should be read as vendor specifications, roadmap targets, or design claims—not as independent benchmark results.
Samsung’s near-term HBM4E target: 3.6 TB/s today, about 4 TB/s at 16 Gbps
Samsung said it began shipping 12-layer HBM4E samples to major global customers in late May. The samples have a stable pin speed of 14 Gbps, with performance scalable to 16 Gbps. Samsung lists 3.6 TB/s of bandwidth and 48 GB of capacity per stack for the 12-layer version. 17
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The company’s planned 16 Gbps-per-pin configuration would push per-stack bandwidth to roughly 4 TB/s. Samsung also outlined 8-layer and 16-layer versions, indicating that HBM4E is intended to serve more than one accelerator and capacity configuration. 18
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That distinction between shipping samples and a higher-speed target matters. The 14 Gbps figure describes the current stable sample specification, while 16 Gbps is the scalable upper performance level Samsung is targeting. The resulting bandwidth numbers are therefore not necessarily interchangeable with a validated production benchmark.
Samsung is moving from standard HBM toward custom memory
Samsung’s roadmap is not limited to increasing DRAM speed or adding more layers. It describes a progression toward cHBM, or custom HBM, in which the base die can be tailored to a customer’s accelerator. That approach gives the memory package a more active role in the overall system rather than treating it as a standardized component. 1
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The longer-term destination is zHBM: a three-dimensional structure that vertically integrates processor logic and DRAM. Samsung’s stated rationale is to remove parts of the conventional 2.5D connection path, including the interposer and SerDes links, which it says could substantially improve efficiency and bandwidth. 1
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Samsung has described zHBM as offering about 70% better power efficiency and more than twice the DRAM bandwidth of the relevant conventional design. Those numbers are projections or company claims about a future architecture, not measurements from a commercially available zHBM product. 1
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Heat is becoming a first-order HBM design constraint
Higher I/O speeds and denser stacks increase the amount of heat that must leave the package. Samsung’s response is its Heat Path Block, or HPB, which creates additional heat-removal paths around high-power physical-layer regions. Samsung said HPB can reduce peak temperature by more than 35% when it covers more than 50% of the PHY area. 10
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Samsung has also said the technology has been implemented and verified in HBM4E, while planning broader integration in HBM5. 4
7 The point is strategically important: cooling is no longer merely a supporting feature of the memory package. It is becoming part of the architecture that determines how quickly the interface can operate.
SK hynix frames HBM scaling as a package problem
SK hynix’s Hot Chips presentation approached the next HBM generations from the manufacturing and integration side. Its analysis compared several ways to connect HBM stacks to accelerators, including large silicon-interposer CoWoS-S, RDL-interposer CoWoS-L, and Intel’s bridge-based EMIB. Each option involves trade-offs in routing, die placement, interposer or substrate size, and package warpage as more memory stacks are placed beside an accelerator. 11
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The company’s current HBM packaging information also illustrates how tightly constrained these designs are. An HBM4 package is described with a 775-micrometer Z-height, along with thousands of TSVs and base-die micro-bumps. As stacks grow taller, designers must manage thinner dies, narrower gaps, mechanical stress, and heat extraction within a fixed package envelope. 11
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SK hynix’s roadmap includes EMIB as one possible 2.5D integration path. That signals technical interest in or compatibility with the packaging approach; it does not, by itself, establish a confirmed commercial partnership between SK hynix and Intel. 12
iHBM targets localized hotspots
SK hynix is also developing iHBM, a cooling approach that places a high-thermal-conductivity material near localized hot spots inside the HBM structure. The company has claimed that the design can reduce thermal resistance by more than 30%. 2
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The contrast with Samsung’s HPB is revealing. Both companies are trying to solve heat at the die-to-die and package level, but their approaches emphasize different physical paths: Samsung describes dedicated heat-transfer structures around PHY regions, while SK hynix focuses on directing heat away from specific internal hot spots. The available reports describe vendor claims and development concepts, so the two percentages should not be treated as directly comparable test results.
Hybrid bonding is the path beyond 16-high stacks—but not yet for HBM4E
Adding more conventional layers eventually runs into a thickness ceiling. SK hynix said hybrid bonding is being researched as a way to move beyond 16-high stacks, potentially enabling taller structures with thicker dies and tighter pitches. 1
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However, the company does not expect hybrid bonding to be ready for HBM4E. The earliest likely target is HBM5, and even that timing remains a development expectation rather than a confirmed product schedule. 2
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This makes HBM5 a potential transition point. HBM4E can increase speed and capacity using current stacking and packaging methods, but future generations may need new bonding, thermal, and mechanical techniques to keep scaling practical.
The key takeaway: bandwidth alone will not decide the next HBM generation
Samsung’s presentation suggests that the next competitive advantage will come from customization and tighter processor-memory integration. Its HBM4E samples provide a near-term speed step, while cHBM and zHBM point toward memory packages designed around specific accelerators and eventually integrated directly with compute. 1
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SK hynix’s message is that those performance gains depend on solving less visible physical problems first: package warpage, thermal resistance, routing density, stack height, and manufacturing yield. Its iHBM and hybrid-bonding work are attempts to extend the useful life of stacked-memory designs without ignoring those constraints. 2
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For AI accelerator designers, the practical conclusion is clear: HBM roadmaps are increasingly about the entire package, not just the DRAM die. Samsung is betting on customization and 3D integration; SK hynix is betting on packaging engineering and manufacturing discipline. Neither path has eliminated the fundamental trade-off between more bandwidth, more heat, and greater integration complexity.
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Samsung’s 12 layer HBM4E samples began shipping to major customers in late May at a stable 14 Gbps per pin, delivering 3.6 TB/s and 48 GB per stack; its planned 16 Gbps version targets roughly 4 TB/s, but these remain...
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Samsung’s 12 layer HBM4E samples began shipping to major customers in late May at a stable 14 Gbps per pin, delivering 3.6 TB/s and 48 GB per stack; its planned 16 Gbps version targets roughly 4 TB/s, but these remain... Samsung’s long term direction is custom cHBM followed by zHBM, which would vertically integrate processor logic and memory; SK hynix is concentrating on package level cooling, warpage, stack height, and interconnect c...
What should I do next in practice?
SK hynix is researching hybrid bonding for stacks beyond 16 layers, but says it is unlikely to be ready for HBM4E and could arrive with HBM5 at the earliest.