At FMS 2026 on August 4, Microchip and Micron jointly demonstrated a validated end to end PCIe Gen 6 storage architecture pairing Microchip's Switchtec Gen 6 fanout switches (3 nm, post quantum secure) with Micron's 9... The architecture is designed for AI, HPC, and hyperscale cloud workloads, enabling composable, d...

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On August 4, 2026, at the Future of Memory and Storage (FMS) Conference in Santa Clara, California, Microchip Technology and Micron Technology jointly demonstrated an end-to-end PCIe Gen 6 storage architecture purpose-built for AI data centers. The live demo combined Microchip's Switchtec Gen 6 PCIe fanout switches with Micron's 9650 NVMe SSDs — the industry's first mass-produced PCIe Gen 6 SSD — to showcase a validated, interoperable stack that can keep AI accelerators fed with data .
The demonstration featured a working configuration in which a Microchip Switchtec Gen 6 PCIe fanout switch served as a high-bandwidth, low-latency interconnect between host processors (CPUs, GPUs, AI accelerators) and multiple Micron 9650 SSDs . The result is a system where several SSDs can run simultaneously at full Gen 6 speeds, rather than sharing a constrained bus
.
Built on a 3 nm process, Microchip's Switchtec Gen 6 PCIe fanout switch acts as a central fabric for composable and disaggregated storage designs . It supports high lane counts, advanced error containment, and multicast one-to-many data distribution. Crucially, it includes a hardware root of trust with post-quantum-safe cryptography compliant with CNSA 2.0 standards, making it suitable for security-conscious cloud and government deployments
.
The Micron 9650 reached mass production in February 2026 and is the world's first commercial PCIe 6.0 enterprise SSD . Key performance figures from its official product brief include
:
| Performance Metric | Micron 9650 Gen 6 | Standard Gen 5 SSD | Advantage |
|---|---|---|---|
| Sequential Read | 28,000 MB/s | 14,000 MB/s | 100% higher |
| Sequential Write | 14,000 MB/s | 10,000 MB/s | 40% higher |
| Random Read | 5.5 M IOPS | 3.3 M IOPS | 67% higher |
| Random Write | 900 K IOPS | 720 K IOPS | 22% higher |
The drive uses Micron's vertically integrated G9 NAND (9th-generation, 276-layer TLC) and a proprietary in-house PCIe Gen 6 controller . It is available in E1.S and E3.S form factors, with the E1.S version supporting liquid cooling for dense server environments
. Power efficiency is also improved: Micron reports 100% higher performance per watt on sequential reads compared to Gen 5, achieving 1,120 MB/s per watt
.
PCIe 6.0 doubles the transfer rate to 64 GT/s per lane over PCIe 5.0, enabling the sustained throughput needed for large AI training, real-time analytics, and high-frequency database workloads . It uses PAM4 signaling and includes low-latency forward error correction (FEC) to maintain signal integrity at these higher speeds.
The FMS 2026 demonstration arrives at a pivotal moment for the PCIe Gen 6 ecosystem. Micron's 9650 has been in mass production since early 2026, giving it clear first-mover status in the enterprise SSD market . At the same conference, Kioxia also demonstrated its CM10 PCIe 6.0 SSD publicly for the first time — built on 332-layer BiCS10 NAND with cold-plate liquid cooling — signaling that competition is heating up
. The event also featured broader industry debates about AI memory tiering and the role of liquid-cooled PCIe 6.0 SSDs in next-generation data centers
.
Microchip's own FMS booth (Booth 415) included technical sessions on SSD error correction optimization for AI workloads, as well as presentations on scaling analog compute-in-memory .
A validating, interoperable PCIe Gen 6 stack like the one demonstrated lowers the integration risk for hyperscalers, potentially accelerating adoption. As a Microchip representative noted, "advancing data center performance is not solved by any single component," positioning the collaboration as a cohesive ecosystem play .
Micron's 9650 targets hyperscalers and large AI data center operators — a high-volume, high-margin customer base . Microchip's Switchtec Gen 6 switches, built on a premium 3 nm node, open a new product cycle in data center infrastructure. At COMPUTEX 2026 earlier in the year, Micron showcased the 9650 as part of its full AI-optimized memory and storage portfolio
.
Micron holds a significant time-to-market lead over rivals like Kioxia in PCIe Gen 6 SSDs, while Microchip's switch technology competes with Broadcom and other PCIe switch vendors . The post-quantum security (CNSA 2.0) and multicast features differentiate Microchip's offering for security-conscious cloud deployments
.
Shares of both Microchip (MCHP) and Micron (MU) jumped on the announcement day, reflecting investor optimism about the PCIe Gen 6 upgrade cycle and the continued AI data center buildout .
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At FMS 2026 on August 4, Microchip and Micron jointly demonstrated a validated end to end PCIe Gen 6 storage architecture pairing Microchip's Switchtec Gen 6 fanout switches (3 nm, post quantum secure) with Micron's 9...
At FMS 2026 on August 4, Microchip and Micron jointly demonstrated a validated end to end PCIe Gen 6 storage architecture pairing Microchip's Switchtec Gen 6 fanout switches (3 nm, post quantum secure) with Micron's 9... The architecture is designed for AI, HPC, and hyperscale cloud workloads, enabling composable, disaggregated storage at PCIe 6.0's 64 GT/s per lane, and represents a significant ecosystem milestone for the upcoming Ge...
Shares of both Microchip (MCHP) and Micron (MU) rose on the announcement day, reflecting investor confidence in the PCIe Gen 6 upgrade cycle and the growing importance of high bandwidth storage for AI data center buil...