Intel used Hot Chips 2026 to present agentic AI as a distributed systems problem rather than a workload for one universal processor. Its three-part portfolio places Diamond Rapids at the server’s orchestration layer, Crescent Island in the inference path, and Wildcat Lake in budget PCs and intelligent edge devices.
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That division reflects how agentic workloads behave: CPUs coordinate tools, memory and workflow state; accelerators generate tokens; and client or edge systems run lower-latency AI locally. Intel has also argued that agentic AI increases the importance of CPU density because the CPU coordinates the reasoning process around accelerator workloads.
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Intel’s three-layer agentic-AI portfolio
| Architecture |
Role |
Key disclosed specifications |
Primary target |
| Diamond Rapids |
Server orchestration and general-purpose compute |
Up to 256 cores, 1.28 GB of last-level cache, 16 memory channels at up to 12,800 MT/s, and 128 PCIe Gen6/CXL 3.0 lanes |
Enterprise servers and accelerator-heavy AI systems |
| Crescent Island |
Inference acceleration |
Xe3P, 32 Xe cores, 256 XMX engines, 160GB reference memory and partner configurations up to 480GB LPDDR5X |
Real-time inference and long-context agentic workloads |
| Wildcat Lake |
Affordable client and edge AI |
Core Series 3 SoC using Panther Cove, Darkmont and Xe3-derived technology |
Budget laptops, thin clients and intelligent edge devices |
The specifications above describe maximum, reference or partner configurations—not necessarily the specification of every commercial SKU.
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Diamond Rapids: a modular Xeon for orchestration
Diamond Rapids is the portfolio’s server-side foundation. Intel described a modular design built from reusable Computer Building Blocks, allowing compute, cache and I/O resources to be combined for different platform requirements instead of relying on one fixed monolithic configuration. A flagship configuration is reported to scale to 256 cores and 1.28 GB of last-level cache, with 16 memory channels supporting rates up to 12,800 MT/s and 128 lanes of PCIe Gen6 and CXL 3.0.
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Those resources are important for agentic systems because the host CPU does more than launch an accelerator kernel. It coordinates model calls, tool use, data movement, security and the application logic connecting multiple steps in an agent workflow. Intel’s own “delivered agents per rack” framing also emphasizes completed work at a specified latency, power and cost—not core count alone.
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18A-P and chiplet packaging
Diamond Rapids’ compute tiles use Intel’s enhanced 18A-P process. Intel positioned the process and the modular architecture as ways to improve scalability and efficiency while accommodating large core counts and extensive memory and I/O connectivity.
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The package is built around multiple dies and chiplet interconnects rather than a single large die. Intel’s Hot Chips materials and related reporting reference Foveros Direct 3D and UCIe-family die connectivity; other reports describe the interconnect as UCIe-S and distinguish it from EMIB. Because Diamond Rapids remains a forward-looking product, the precise package configuration should be treated as a disclosed design direction rather than a final shipping specification.
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Intel has not provided final clocks, pricing or a complete SKU breakdown in the material available here. Reporting points to a 2027 data-center release, so Diamond Rapids is best understood as a platform preview rather than an immediately available Xeon product.
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Crescent Island: inference capacity without HBM
Crescent Island is a different kind of bet. Rather than competing as a graphics-first or training-first GPU, Intel designed it as a PCIe accelerator for inference, with an emphasis on token generation, real-time response and long-context agentic models. The card uses the Xe3P architecture with 32 Xe cores and 256 XMX engines.
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The reference card is specified with 160GB of LPDDR5X memory, while partner boards can scale to 480GB. It is designed as a 350-watt, air-cooled PCIe card, with reporting identifying a PCIe Gen5 x16 interface.
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Why LPDDR5X instead of HBM?
The memory choice is central to Crescent Island’s positioning. HBM offers substantially more bandwidth, but it also brings cost, advanced-packaging and power or cooling trade-offs. Intel’s alternative is to provide large memory capacity using LPDDR5X in a card that can fit conventional air-cooled server infrastructure. That makes the product’s target less about peak benchmark performance and more about the economics of hosting larger models and producing tokens within a manageable power envelope.
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This does not make LPDDR5X a universal replacement for HBM. Workloads that are dominated by memory bandwidth may still favor a higher-bandwidth design. Intel’s stated opportunity is the inference segment, where model capacity, cost per token, power efficiency and deployment simplicity can be more important than maximum bandwidth. Performance claims remain difficult to evaluate because Intel has not disclosed complete application-level performance figures in the available sources.
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Intel planned customer sampling in the second half of 2026. Separate reporting expects broader availability in 2027, but that is not the same as a confirmed general-availability date from Intel.
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Wildcat Lake: lower-cost AI for PCs and the edge
Wildcat Lake, marketed as Intel Core Series 3, covers the lower end of Intel’s client and edge strategy. It is aimed at value laptops, commercial systems, thin clients and intelligent edge devices rather than high-end AI workstations.
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The SoC reuses technology from Intel’s broader client portfolio, including Panther Cove performance cores, Darkmont efficient cores and Xe3 graphics technology. Reusing established IP gives Intel a simpler path to lower-cost platforms while retaining CPU, GPU and NPU resources for local or hybrid AI features.
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Wildcat Lake is also notable for its packaging trade-off. It is described as Intel’s first processor to use UCIe for an internal chiplet connection. Instead of the more complex Foveros approach used in higher-end designs, Wildcat Lake uses a two-die organic multi-chip package, with UCIe providing the die-to-die link. That choice is better aligned with cost-sensitive, high-volume systems.
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Intel has reported more than 70 laptop designs for the Core Series 3 family through 2026, an early market milestone for the value-oriented platform. The design-win figure indicates OEM interest, but it does not by itself establish shipment volume or end-user adoption.
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What Intel’s strategy means
Intel’s Hot Chips presentation was less a single-product launch than a division of labor across the computing stack:
- Diamond Rapids supplies dense host compute, memory and I/O for coordinating enterprise AI systems.
- Crescent Island addresses inference capacity, especially when memory capacity and air-cooled operation matter more than maximum bandwidth.
- Wildcat Lake extends local AI capabilities into more affordable PCs and edge platforms.
The architecture choices follow that segmentation. Diamond Rapids uses a highly modular server design; Crescent Island trades HBM bandwidth for capacity and deployment economics; and Wildcat Lake uses reused client IP, UCIe and organic packaging to control platform cost.
The important qualification is timing. Diamond Rapids is associated with a 2027 data-center release, Crescent Island is moving toward second-half-2026 sampling with broader availability expected later, and Wildcat Lake has the clearest near-term OEM milestone through its scheduled 2026 laptop designs. Final prices, clocks, product segmentation and production availability could still change as these road-map products move toward shipping systems.
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