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IBM’s Next Mainframe Chip Brings Native Arm Support to Every Core
IBM unveiled a future, unnamed 2nm processor with 11 cores above 5.7 GHz, and every core is designed to execute both IBM z/Architecture and Arm AArch64 instructions. The design uses KVM to switch between IBM Z and Arm execution modes in nanoseconds, allowing Arm native Linux workloads to coexist with z/OS and Linux...
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Key takeaways
- IBM unveiled a future, unnamed 2nm processor with 11 cores above 5.7 GHz, and every core is designed to execute both IBM z/Architecture and Arm AArch64 instructions.
- The design uses KVM to switch between IBM Z and Arm execution modes in nanoseconds, allowing Arm native Linux workloads to coexist with z/OS and Linux on IBM Z without separate Arm and IBM core clusters.
- AI inference accelerators, an on chip data processing unit and large caches are intended to extend IBM Z and LinuxONE into newer cloud native and AI workloads.
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openai.comCreate a landscape editorial hero image for this Studio Global article: What did IBM unveil at the Hot Chips 2026 conference in partnership with Arm—a first-of-its-kind dual-architecture mainframe processor for f. Article summary: IBM unveiled an as-yet-unnamed dual-architecture processor for future IBM Z and LinuxONE systems, developed with Arm. Its key innovation is that every core—not separate clusters of IBM and Arm cores—can natively execute . Topic tags: general, general web, documentation. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks, charts with fak
IBM has unveiled a future dual-architecture processor for IBM Z and LinuxONE systems, developed in collaboration with Arm. Its defining feature is not simply support for two processor families on one package: each of the planned chip’s 11 cores is designed to natively execute both IBM’s z/Architecture and Arm’s 64-bit AArch64 instruction set. 1
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That could let enterprises place Arm-native Linux software alongside established z/OS and Linux on IBM Z workloads on the same mainframe platform. The goal is to make newer applications and AI software easier to bring to mission-critical infrastructure without forcing customers into extensive application-by-application ports. 3
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What IBM announced
The processor is still an unnamed design rather than a commercial product. IBM presented it at Hot Chips 2026 as a processor for future IBM Z and LinuxONE systems, with an expected system timeframe reported as around 2028. IBM has not announced a final product name, and the company cautions that statements about future direction and intent can change or be withdrawn. 6
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The headline specifications and capabilities announced or reported so far include:
- 11 high-performance cores built using a 2-nanometer process.
- Clock speeds of more than 5.7 GHz.
- Native execution of both IBM z/Architecture and Arm AArch64 instructions on every core.
- Integrated AI inference accelerators.
- An on-chip data-processing unit for I/O acceleration.
- A large cache design intended for demanding enterprise transaction and data workloads.
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The broader IBM Z and LinuxONE systems are intended to scale beyond the processor itself, including configurations with hundreds of cores and tens of terabytes of memory. 7
How the dual-architecture design works
A conventional heterogeneous design might place Arm cores and IBM Z cores in separate groups. IBM’s approach is different: the same core can execute either instruction set natively, rather than relying on a separate Arm cluster or software emulation. 1
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The processor is intended to support two execution modes:
- IBM Z mode, for z/Architecture workloads and operating environments such as z/OS.
- Arm mode, for Arm-native Linux binaries and applications built for AArch64.
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IBM says the core can switch between those modes in nanoseconds through the open-source KVM hypervisor. Christian Jacobi of IBM described the switching overhead as effectively amortizing to zero, although real-world performance will ultimately need to be demonstrated on production hardware and workloads. 1
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This distinction matters. The announcement describes native instruction execution, not translation of every Arm instruction into IBM Z instructions. It also does not mean that one software process automatically changes instruction sets mid-operation; rather, the platform is designed to schedule workloads in the appropriate execution environment while allowing both software ecosystems to share the system. 1
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Why Arm support matters for IBM Z
Arm has become an important target for Linux software, infrastructure tools and machine-learning frameworks. Existing documentation shows Arm support for PyTorch and ONNX Runtime, while ONNX Runtime can run models originating in frameworks such as PyTorch. 17
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That gives IBM a way to position future Z and LinuxONE systems for software that customers may already be developing for Arm-based cloud and server environments. The intended benefit is less about replacing IBM’s established software stack and more about adding another execution environment beside it.
In practical terms, an organization could continue running long-lived z/OS applications and existing Linux on IBM Z workloads while deploying compatible Arm-native Linux applications on the same broader platform. IBM’s announcement frames this as a way to expand the ecosystem around its mission-critical systems while maintaining their enterprise focus on availability, security, encryption, reliability and scale. 7
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Where AI acceleration fits
The processor is also designed with AI inference in mind. IBM has described dedicated inference acceleration alongside the dual-ISA CPU cores, while reporting from the Hot Chips presentation points to a second-generation on-chip AI accelerator intended for larger enterprise inference workloads. 7
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The combination is strategically significant: Arm-native Linux makes more software available to the system, while dedicated inference hardware could reduce the need to handle every AI operation on general-purpose CPU cores. However, IBM has not yet published production benchmarks in the supplied announcement materials, so the chip’s eventual performance, energy efficiency and software compatibility remain open questions.
The strategic trade-off
The central promise is application flexibility. Without native support for Arm software, moving modern applications onto an IBM Z or LinuxONE environment can require porting, rebuilding or otherwise adapting software for the platform’s instruction set. IBM is presenting the dual-architecture processor as a way to reduce that friction. 3
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The design could therefore appeal to organizations that want to keep core transaction systems on mainframes while bringing newer cloud-native services, AI inference and Arm-targeted applications closer to those systems. The potential advantage is architectural coexistence rather than a forced migration from one software world to another.
That promise still depends on more than silicon. Operating-system support, hypervisor behavior, tooling, application dependencies, licensing and workload-specific performance will determine how seamless the experience is. The available evidence describes IBM’s design intent, not a completed product evaluation.
What remains unknown
IBM has not disclosed a commercial name for the processor, and it is not a shipping chip. The reported launch window around 2028 should be treated as an expectation rather than a guaranteed release date. 6
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The company’s own qualification is important: future-product statements describe goals and objectives, and may change. Until IBM provides final specifications, systems and benchmarks, the most defensible conclusion is that it has revealed an ambitious dual-ISA direction for its next generation of mainframe hardware—not a finished replacement already available to customers.
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What is the short answer to "IBM’s Next Mainframe Chip Brings Native Arm Support to Every Core"?
IBM unveiled a future, unnamed 2nm processor with 11 cores above 5.7 GHz, and every core is designed to execute both IBM z/Architecture and Arm AArch64 instructions.
What are the key points to validate first?
IBM unveiled a future, unnamed 2nm processor with 11 cores above 5.7 GHz, and every core is designed to execute both IBM z/Architecture and Arm AArch64 instructions. The design uses KVM to switch between IBM Z and Arm execution modes in nanoseconds, allowing Arm native Linux workloads to coexist with z/OS and Linux on IBM Z without separate Arm and IBM core clusters.
What should I do next in practice?
AI inference accelerators, an on chip data processing unit and large caches are intended to extend IBM Z and LinuxONE into newer cloud native and AI workloads.