Huawei’s Tau Scaling Law Shifts Chip Progress From Smaller Transistors to Faster Signals

Huawei used the 2026 IEEE International Symposium on Circuits and Systems in Shanghai to present what it calls the Tau (τ) Scaling Law. In a keynote titled “New Semiconductor Path in Practice,” He Tingbo argued that future chip progress should depend less on physically shrinking transistors and more on reducing the time signals and workloads need to move through electronic systems. 23

The proposal is best understood as a design framework, not a new manufacturing process. Huawei links it to LogicFolding, software–hardware co-optimization and system interconnect technologies intended to improve performance, energy efficiency and effective transistor density as conventional geometric scaling becomes harder to sustain. 12

From smaller transistors to shorter delays

Traditional scaling measures progress largely through smaller transistor dimensions and higher transistor density. Huawei’s proposed τ scaling instead makes signal-propagation delay and overall execution time central optimization targets. The company says that reducing delays across the technology stack could deliver gains even when transistor shrinkage slows. 235

That does not make transistor size irrelevant. Rather, Huawei is proposing a broader definition of progress—one that also considers resistance, capacitance, wiring, architecture and data movement, all of which influence how quickly a system can perform useful work.

How Huawei says Tau scaling works

Huawei describes the approach as coordinated optimization across four levels.

1. Device level: reducing resistance and capacitance

At the device and interconnect level, the goal is to reduce resistance and parasitic capacitance. These electrical properties contribute to signal delay and energy consumption, so improving them can shorten the time constants of transistors and the connections between them. 2

2. Circuit level: shortening critical paths

At the circuit level, Huawei focuses on shortening critical-path wiring and reducing resistive and capacitive loading. The intended result is faster signal movement through logic and lower energy use for each operation. LogicFolding is presented as one of the technologies supporting this part of the strategy. 25

3. Chip level: coordinating software, architecture and silicon

The proposal goes beyond isolated circuit improvements. At the chip level, Huawei calls for software, architecture and silicon to be designed together around real workloads. That means optimizing instruction flow, data flow and parallel execution instead of treating raw transistor count as the only meaningful measure of capability. 2

4. System level: treating communication as part of scaling

At the system level, Huawei connects τ scaling with its UnifiedBus interconnect and “cluster + SuperPoD” architecture. Huawei says UnifiedBus is designed for large AI training and inference systems, connecting processors with high bandwidth, low latency and unified memory addressing so the infrastructure can operate more like a single logical computer. 17

These are architectural goals and company claims, not independently established industry standards. Their relevance to Tau scaling is straightforward: communication between chips and servers becomes part of the performance equation. Cutting interconnect delays can improve the effective speed of an entire system even when individual transistors are not dramatically smaller.

Huawei’s reported deployment and roadmap

Huawei said it had applied the Tau Scaling Law to smartphone and AI-computing products and had designed and mass-produced 381 chips based on the approach over the previous six years. That figure comes from Huawei’s own disclosure. 2

The company also said that Kirin smartphone chips planned for fall 2026 would be the first to fully adopt its LogicFolding architecture. 257

Huawei’s longer-term target is for high-end chips designed under the framework to reach transistor density equivalent to a 14 Å, or 1.4nm, process by 2031. This is a density-equivalence goal—not evidence that Huawei has already produced an independently verified 1.4nm manufacturing process. 251231

He Tingbo also called for openness and cooperation among scientists, engineers and industry partners, presenting semiconductor progress as a challenge that cannot be solved by one company alone. 2

Is Tau Scaling a replacement for Moore’s Law?

Not yet. Huawei is positioning τ scaling as a successor or alternative guiding principle because the historical gains from transistor shrinkage have become more difficult and expensive. But calling it a “law” does not make it a universally accepted physical law, and the available reporting does not independently verify all of Huawei’s projected performance, efficiency or density gains.

The underlying engineering ideas—reducing resistance, capacitance, wiring delay, data movement and system communication overhead—are familiar forms of optimization. Huawei’s distinct claim is that these techniques should be coordinated and used as the industry’s primary scaling framework across devices, circuits, chips and complete computing systems. 1219

Why the announcement matters

The proposal reflects a broader shift in advanced computing. As leading-edge process improvements slow, performance increasingly depends on architecture, packaging, memory movement, interconnects and workload-specific software. Tau scaling is therefore less a claim that geometry no longer matters than an argument that time-to-compute should matter alongside transistor dimensions.

The practical test will be whether upcoming Kirin and AI products can demonstrate measurable gains from LogicFolding and the wider τ-scaling approach. Until those results are independently assessed, Huawei’s announcement is best read as an ambitious semiconductor roadmap—not proof that Moore’s Law has already been replaced.