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Axera M9 ADAS Chips: M97 at 720 TOPS, M95 at 360 TOPS
Axera’s September 15 coverage highlighted its 5nm M9 ADAS family: the M97 delivers 720 TOPS for high end urban NOA and larger driving models, while the M95 delivers 360 TOPS for mainstream one stage end to end systems. The M97 offers 16 Cortex A78AE CPU cores, 460 GB/s equivalent memory bandwidth and up to 16 camera...
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Key takeaways
- Axera’s September 15 coverage highlighted its 5nm M9 ADAS family: the M97 delivers 720 TOPS for high end urban NOA and larger driving models, while the M95 delivers 360 TOPS for mainstream one stage end to end systems.
- The M97 offers 16 Cortex A78AE CPU cores, 460 GB/s equivalent memory bandwidth and up to 16 camera inputs; the M95 has 10 cores, 260 GB/s bandwidth and up to 14 camera inputs.
- M97 engineering samples were delivered in the first half of 2026 and several OEMs had begun evaluation and selection processes; this is not the same as confirmed broad vehicle deployment.
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openai.comCreate a landscape editorial hero image for this Studio Global article: What did Axera announce on September 15, 2026 about its 5nm automotive-grade M9 ADAS SoC series—specifically the flagship M97’s approximatel. Article summary: Axera’s September 15 coverage described the M9 as a two-chip, 5nm automotive ADAS platform: the flagship M97 at about 720 TOPS for high-end urban NOA, VLA/world-model and cockpit-plus-driving use, and the M95 at about 36. Topic tags: general, general web. Style: premium digital editorial illustration, source-backed research mood, clean composition, high detail, modern web publication hero. Use reference image context only for broad subject, composition, and topical grounding; do not copy the exact image. Avoid: logos, brand marks, copyrighted characters, real person likenesses, fake screenshots, UI text, readable text, watermarks, charts with fake numbers, clic
Axera introduced the M9 as a two-tier, 5nm automotive advanced driver-assistance system-on-chip family: the flagship M97 (M9x-720T) with 720 TOPS of equivalent AI compute, and the mainstream M95 (M9x-360T) with 360 TOPS. The formal launch was September 8, while the September 15 coverage recapped the announcement and its positioning. 11
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The central idea is portability: Axera says both chips share an architecture, toolchain and reusable software assets, allowing automakers and Tier-1 suppliers to scale an assisted-driving application across performance tiers without rebuilding it from scratch. 11
M97 vs. M95: the practical split
| Specification | M97 | M95 |
|---|---|---|
| Process | 5nm automotive-grade | 5nm automotive-grade |
| Advertised equivalent AI compute | 720 TOPS | 360 TOPS |
| CPU | 16 Arm Cortex-A78AE cores | 10 Arm Cortex-A78AE cores |
| Equivalent memory bandwidth | 460 GB/s | 260 GB/s |
| Memory configurations | 36 / 48 / 64 / 96 GB | 12 / 18 / 24 GB |
| ISP input | Up to 16 cameras; 4.5 gigapixels/s | Up to 14 cameras; 2.6 gigapixels/s |
M97 is intended for flagship vehicle platforms, including urban navigate-on-autopilot (NOA), VLA and world-model-style workloads, and combined cockpit-and-driving perception. M95 is positioned for the more cost-sensitive, mainstream market for one-stage end-to-end driving systems. 7
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Both chips are described as meeting AEC-Q100 automotive requirements, with an on-chip ASIL-D lockstep safety island and an overall ASIL-B rating. They also support dual-chip redundant configurations. 4
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What Axera says is inside the M9 platform
The M9 designs combine three self-developed processing blocks: an NPU for AI inference, an ISP for camera processing, and a computer-vision accelerator (CVA) for preprocessing and sensor tasks.
NPU: model flexibility and data movement
Axera says its NPU uses a functional-safety-oriented, multi-core and multi-cluster design. It supports FP4, INT8, FP8 and BF16 precision formats, and the company claims hardware-level CPU-to-NPU zero-copy transfer to reduce data movement. Axera also says its toolchain can shorten algorithm adaptation from months to weeks. 21
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Those are product claims, not results from a standardized independent benchmark. They matter because large perception and planning models can be constrained as much by memory traffic and integration work as by headline TOPS figures.
ISP: two outputs from one camera stream
The ISP is designed around a dual-pipeline approach: one machine-vision path is optimized for AI perception, while a separate human-vision path is optimized for display quality. For the M97, Axera claims sub-10-millisecond ISP latency, up to 16 camera inputs and 4.5 gigapixels per second of throughput. 21
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CVA: offloading visual and sensor work
The CVA is intended to handle work such as image preprocessing, computer-vision operators, LiDAR point-cloud processing and multi-sensor time synchronization. Axera’s stated goal is to keep these tasks from consuming CPU and NPU resources, leaving more of the NPU available for inference. 11
Dual-chip designs and claimed performance
Axera has positioned M9 for dual-chip redundancy as well as cockpit-plus-driving board configurations. The company says a two-M97 design can reach roughly 1,440 TOPS, while a dual-M95 setup is quoted at 720 TOPS. 11
The company also reports that its M9 systems exceed “industry level” frame rates by more than 1.5×; it says M95 end-to-end performance exceeds an industry average by more than 2×, M97 VLA performance is more than 1.5× higher, and ISP-path latency is about 70% lower. 18
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These comparisons should be read cautiously. The available reporting attributes them to Axera’s internal testing and does not identify independent third-party ADAS benchmarks that validate the results across the same models, sensors, software stacks and operating conditions.
An open compute-base strategy
Axera says it will remain a compute-base supplier rather than build upper-layer intelligent-driving algorithms that could compete with automakers and Tier-1 suppliers. In principle, that gives customers control over the algorithms and driving stack they deploy on M9 hardware. 8
The company also reported cumulative global intelligent-driving-chip shipments above 1.6 million units through August 2026, with its prior M5 family already in volume vehicle production. 8
Readiness: samples and OEM evaluation, not broad deployment
M97 was brought up after wafer return in February 2026, and engineering samples were delivered in the first half of the year. Axera’s Hong Kong exchange disclosure said several leading automotive OEMs had formally started solution evaluation and selection. M95 was brought up in July 2026. 5
That establishes a meaningful development milestone, but it does not confirm broad M97 vehicle deployment. For buyers and investors, the next evidence to watch is named design wins, production schedules and independently comparable real-world performance—not just peak compute figures or internal frame-rate claims.
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What is the short answer to "Axera M9 ADAS Chips: M97 at 720 TOPS, M95 at 360 TOPS"?
Axera’s September 15 coverage highlighted its 5nm M9 ADAS family: the M97 delivers 720 TOPS for high end urban NOA and larger driving models, while the M95 delivers 360 TOPS for mainstream one stage end to end systems.
What are the key points to validate first?
Axera’s September 15 coverage highlighted its 5nm M9 ADAS family: the M97 delivers 720 TOPS for high end urban NOA and larger driving models, while the M95 delivers 360 TOPS for mainstream one stage end to end systems. The M97 offers 16 Cortex A78AE CPU cores, 460 GB/s equivalent memory bandwidth and up to 16 camera inputs; the M95 has 10 cores, 260 GB/s bandwidth and up to 14 camera inputs.
What should I do next in practice?
M97 engineering samples were delivered in the first half of 2026 and several OEMs had begun evaluation and selection processes; this is not the same as confirmed broad vehicle deployment.