AMD’s MI455X and Helios: Inside the MI400 Rack-Scale AI Strategy

AMD used Hot Chips 2026 to make a broader argument than “faster GPU.” Its MI400 generation is being positioned as the silicon foundation for rack-scale AI, with the MI455X accelerator, EPYC server CPUs, Pensando networking, high-speed fabric and ROCm software designed as a coordinated system. 467

That distinction matters because large AI deployments are constrained not only by accelerator compute, but also by memory capacity, memory movement, scale-up communication, networking and software portability.

MI455X: a chiplet accelerator built for AI workloads

The MI455X is AMD’s flagship accelerator in the fifth-generation CDNA family. AMD describes it as a chiplet design that combines eight TSMC N2 compute dies with N3P fabric, cache and I/O dies, connected through CoWoS-L advanced packaging. 27

The accelerator is specified with 256 work-group processors and native Wave32 execution. AMD also highlighted a lower-latency transcendental-function engine, an architectural change aimed at improving the handling of operations used across training, inference and fine-tuning workloads.

Memory is one of the MI455X’s defining features. Twelve HBM4 stacks provide 432 GB of capacity and 23.3 TB/s of stated bandwidth per GPU. 257 AMD quotes peak throughput of 40.26 petaflops for MXFP4, plus 20.13 petaflops each for MXFP6 and MXFP8. Those numbers describe theoretical formats and peak specifications, rather than independent application performance.

Helios makes the rack the deployment unit

AMD’s Helios strategy takes the MI455X out of the traditional “single accelerator” frame. The planned Open Rack Wide-based system connects 72 MI455X GPUs in one rack-scale configuration. AMD and related coverage describe the system as delivering up to 2.9 exaflops of FP4 performance and roughly 31 TB of aggregate HBM4. 1347

The published bandwidth figures require some care. ServeTheHome’s Hot Chips reporting describes approximately 1.7 PB/s of aggregate HBM4 bandwidth using the newer 23.3-TB/s-per-GPU figure. 7 Earlier CES coverage cited 1.4 PB/s for the same 72-GPU Helios concept. 4910 The difference may reflect a revised specification, a different measurement basis or a change in how the system was described. It should not be treated as a directly comparable benchmark result without further clarification.

AMD also cites 260 TB/s of scale-up bandwidth across the 72-GPU domain. 47 The objective is to keep a large accelerator pool sufficiently connected for frontier-model training and inference, rather than treating each GPU as an isolated device.

What sits inside a Helios compute tray?

The system architecture is built from three co-designed silicon blocks:

• MI455X: the primary AI compute and HBM4 component.
• EPYC “Venice” host CPU: a 9006-series EPYC processor using the SP7 platform; Hot Chips coverage describes a 96-core configuration. 46
• Pensando Vulcano AI NIC: the networking component for scale-out communication and data movement. 6

A compute tray combines four MI455X modules with an EPYC host processor and can include up to three Pensando Vulcano 800 AI NICs. 46 AMD’s UALoE fabric links the components inside the broader platform, while the networking layer connects the rack to the rest of the data center.

This arrangement reflects AMD’s full-system approach: CPUs handle host and orchestration work, GPUs provide dense AI compute, and dedicated networking silicon helps move data without making the accelerator do every communication task itself.

ROCm is the software counterweight to CUDA

Hardware alone does not make a competitive AI platform. AMD is therefore presenting ROCm as the software foundation for the MI400 family and Helios. The company describes ROCm as an open, AMD software-based stack spanning hyperscale AI, high-performance computing, research and sovereign deployments. 1

The strategic goal is to give customers an alternative to a CUDA-dependent GPU stack. That does not mean software compatibility is solved automatically: real-world adoption depends on framework support, optimized kernels, developer tools, libraries and performance on specific workloads. Still, the positioning is clear—AMD wants ROCm to be part of the platform decision, not an afterthought once the hardware has been selected. 17

The wider AMD strategy extends beyond GPUs

AMD’s Hot Chips message also fits into a wider portfolio strategy involving CPUs, GPUs, networking products, adaptive SoCs and FPGAs. The company is presenting these components as building blocks for data-center AI, physical AI, edge processing and mission-critical systems rather than as disconnected product categories. 11214

The Versal Premium Gen 2 Memory-on-Package family illustrates the non-GPU side of that strategy. The devices integrate up to 32 GB of LPDDR5X into the package and provide up to 288 GB/s of memory bandwidth, while AMD says the design can reduce board area by up to 60% compared with external-memory implementations. 3237

They also include hard IP for CXL 3.1 and PCIe 6.0, along with security features such as PCIe Integrity and Data Encryption, inline memory encryption and ECC. Hot Chips coverage additionally describes a security roadmap involving PCIe Gen 7 capabilities and post-quantum cryptography. 373943

These products do not replace the MI455X. They show how AMD is trying to cover different points in the infrastructure stack: dense accelerator compute for large AI systems, general-purpose CPU capacity, programmable logic and adaptive processing for specialized or edge workloads, and networking and security silicon for moving and protecting data.

What the Hot Chips announcement means

The most important takeaway is architectural rather than numerical. AMD is arguing that the effective unit of AI infrastructure is increasingly the connected rack, not the individual GPU.

The MI455X supplies the compute density and HBM4 capacity. Helios supplies the rack-level interconnect, host processors and networking. ROCm supplies the software layer AMD hopes will make the system practical to deploy across multiple customer environments. The broader CPU, FPGA, adaptive SoC and networking portfolio gives AMD more ways to participate in the same infrastructure buildout.

AMD has positioned MI455X and Helios volume deployments for the second half of 2026. 315 Until systems ship and independent workload benchmarks become available, the most defensible reading is that AMD has presented an ambitious platform specification and roadmap—not proof that Helios will outperform competing systems across real-world applications.