Inside Peking University's 3D EDA Tool for Huawei's 'Logic Folding' Chip Ambitions

The strategic importance of this software is impossible to understand without looking at the EDA market. Every advanced chip on Earth is designed using EDA software from three companies: Synopsys, Cadence, and Siemens EDA . These three firms act as the irreplaceable bridge between a chip's functional requirements and what a foundry can physically manufacture, translating billions of transistors into manufacturable silicon . Together, the "Big 3" hold over 85% of the global EDA market, with Synopsys alone generating an estimated $8 billion in 2025 revenue after its acquisition of Ansys .

The market's structure is hardened oligopolistic, maintained through decades of proprietary algorithms, deep customer lock-in, and aggressive mergers and acquisitions . The global chip design software market was valued at roughly $8.46 billion in 2025, with gross margins between 80% and 95% . For Chinese firms like Huawei, this concentration represents a strategic choke point. Export controls have already restricted Huawei's access to the most advanced versions of these Western tools, and losing access entirely would sever the connection between chip design and manufacturing.

Peking University's tool directly targets this vulnerability for Huawei's specific architectural path. The South China Morning Post described the software as compatible with Huawei's LogicFolding architecture, framing it as part of an accelerating, coordinated push by the Chinese government, industry, and academia toward technological self-reliance . This is not China's first EDA milestone. In 2023, Huawei announced it had completed the localization of EDA tools for chips above 14 nanometers in partnership with domestic companies . In 2024, Chinese firm X-EPIC introduced EDA software that could run on domestically produced processors from Huawei and Phytium .

What makes the 2026 Peking University announcement different is its focus on a forward-looking, three-dimensional architecture that does not yet exist in commercial products. It is a bet on a specific trajectory—one where performance gains come from design cleverness rather than access to restricted manufacturing nodes—and a prototype tool to prove that trajectory is viable. Whether Logic Folding and the domestic EDA ecosystem can truly match the capabilities of the Synopsys-Cadence-Siemens triad on a commercial scale remains an open question, but the blueprint is now public.