TSMC’s Reported 2nm and 3nm Capacity Ramp Through Mid-2027

Reports point to an aggressive expansion of TSMC’s leading-edge chip output as AI and high-performance computing customers seek more 3nm and 2nm capacity. The headline figures—while not confirmed directly by TSMC—are 110,000 2nm wafers per month and 210,000 3nm wafers per month by mid-2027. 17

The reported mid-2027 capacity targets

According to supply-chain reporting cited by TrendForce, TSMC’s 2nm monthly capacity would grow from roughly 90,000 wafers at the end of 2026 to 110,000 by mid-2027, an increase of about 22%. The same reporting puts 3nm capacity at more than 180,000 wafers per month by end-2026 and 210,000 by mid-2027—an increase of more than 16% over that period. 17

The longer 3nm comparison is even larger: output is reported to rise from about 120,000–130,000 wafers per month at the end of 2025 to 210,000 by mid-2027, or roughly 70% if the plan is achieved. 20

Those numbers should be read as reported targets, not company guidance. The reports trace them to supply-chain sources, and TSMC has not publicly validated the specific 2nm and 3nm monthly-capacity figures. 1719

How Taiwan, Arizona and Japan support the expansion

Taiwan remains the core of the near-term leading-edge ramp. Reporting identifies TSMC’s Fab 22 in Kaohsiung as part of the N2/A16 expansion, while Fab 20 in Hsinchu is also listed as ramping N2 and A16 capacity. 51

For 3nm, reports say TSMC is converting some existing 5nm equipment in Taiwan to 3nm use. Reusing and reconfiguring qualified manufacturing infrastructure can add output faster than relying solely on entirely new fabs, though TSMC has not publicly detailed the equipment allocation by facility. 24

The overseas footprint is broadening as well:

• Arizona: The first fab has begun 4nm production, while later phases are planned around 3nm, 2nm and A16-class technologies. TSMC has also announced an additional $100 billion investment for more U.S. wafer fabs and advanced-packaging capacity. 4538
• Japan: TSMC’s Kumamoto operation is expanding with a second fab expected to support technologies down to 3nm, according to reporting on the company’s manufacturing roadmap. 51
• Reported global 3nm additions: A separate report says the company is adding 3nm facilities across Taiwan, Arizona and Japan alongside Taiwan tool conversions. 33

The exact timing and share of capacity from each site remain less clear than the aggregate wafer targets. The cleanest conclusion is that Taiwan is central to the immediate ramp, with Arizona and Japan extending TSMC’s geographic manufacturing base over time.

AI demand is driving the investment cycle

TSMC increased its 2026 capital-expenditure plan to $60 billion–$64 billion, citing multiyear structural demand from AI and high-performance computing. The company said it was accelerating its global footprint, including leading-edge and advanced-packaging fabs in Taiwan plus expansions in Arizona, Japan and Germany. 38

The funding matters because advanced-node supply is not simply a question of wafer-fab floor space. It requires lithography, process tools, qualified materials, yield learning and packaging capacity that can keep pace with increasingly large AI processors.

CoWoS packaging is part of the bottleneck

Leading-edge logic dies alone are insufficient for many AI accelerators. They also need advanced packaging to connect compute dies and high-bandwidth memory, which is why TSMC’s CoWoS packaging expansion is closely linked to its wafer-fab plans.

TrendForce reported that CoWoS capacity could approximately double by 2028, though that is also a supply-chain-based estimate rather than a directly confirmed TSMC target. 17 TSMC has separately said its CoWoS capacity is forecast to grow at a compound annual rate above 80% from 2022 to 2027. 45

Arizona is expected to become part of that packaging network: TSMC plans to open an Arizona chip-packaging plant by 2029, according to a company executive cited by Reuters. 47

The roadmap after 2nm: A14, A13 and A12

TSMC’s public technology roadmap reaches beyond the N2 family:

• A14: TSMC has scheduled its 1.4nm-class A14 process for production in 2028. 11
• A13: The 1.3nm-class A13 is slated for 2029 and is described as a derivative of A14 aimed at client-oriented applications. 10
• A12: Also targeted for 2029, A12 builds on the A16 path for HPC and AI and uses backside power delivery. 10
• N2U: TSMC also plans an N2-family extension, N2U, for 2028. 10

This makes the reported 2nm and 3nm expansion more than a short-term capacity response. It is the manufacturing base from which TSMC intends to move into successive sub-2nm process generations.

ASML, High-NA EUV and 12-inch photomasks

TSMC and ASML have formally launched an industry initiative to transition High-NA EUV lithography from today’s 6-inch photomasks toward 12-inch photomasks. The partners target a 12-inch mask pilot line by 2031 and supporting lithography-system readiness for advanced-node production by 2033. 2

High-NA EUV can enter production using existing 6-inch masks first; the larger-mask transition is intended to improve fab productivity, reduce chipmaking costs and address stitching constraints. 2 Reporting says TSMC plans High-NA EUV high-volume manufacturing from 2030, placing it after the announced A14, A13 and A12 production milestones rather than as a prerequisite for those initial nodes. 311

What to watch

The core takeaway is straightforward: TSMC is investing across wafer fabrication and advanced packaging to serve sustained AI and HPC demand. Its capital-expenditure increase, Arizona expansion and longer technology roadmap are publicly reported or announced. 384711

The attention-grabbing monthly targets—90,000 to 110,000 for 2nm, and more than 180,000 to 210,000 for 3nm—remain supply-chain reports. They are useful indicators of the scale and pace expected through mid-2027, but they should not be treated as confirmed TSMC capacity guidance unless the company provides a direct update. 1719