Who Is Leading the High-NA EUV Race? Intel Ships First Volume Chips as Samsung and TSMC Hold Back

Intel has also hinted at further adoption: it is expected to use High-NA EUV at its upcoming 14A node as well .

Samsung: Targeting 1nm (A10) Around 2030

Samsung's timeline has shifted significantly. At the 2026 NGL conference, Samsung VP of Technology ChangMin Park stated the company plans to adopt High-NA EUV as its primary manufacturing technology starting at the 1nm (A10) node, around 2030 . Samsung had hoped to introduce the tool at 2nm and 1.4nm, but further technical improvements are needed .

• Interim nodes (2nm, 1.4nm, early 1nm): These will continue to rely on conventional 0.33 NA EUV with multiple patterning; Samsung has explicitly ruled out High-NA for those nodes .

Despite this cautious production timeline, Samsung has already installed two High-NA EUV systems — one at its Hwaseong campus in 2025 and a second in H1 2026 — representing an investment of over KRW 1 trillion . However, the company is holding back on mass-production deployment to contain costs .

Reports earlier in 2025 had suggested Samsung might deploy High-NA at 2nm for chips like the Exynos 2600 and Tesla's next-generation AI chips . Latest statements from Samsung's executives directly contradict that earlier expectation .

TSMC: Deferring Until at least 2029

TSMC is the most cautious of the three. CEO C.C. Wei stated on the Q2 2026 earnings call that the company does not need High-NA for nodes from 2nm (N2) through A16 and A14, and that adoption depends on technical capability, customer cost sensitivity, and equipment maturity .

• Target node and year: Reports indicate TSMC's A13 and A12 nodes (both targeted around 2029) are not expected to require High-NA EUV . Some analysts say meaningful volume deployment may not happen until A14 in 2028 or later, but even that timeline has been challenged by management's public statements .
• Key reason: TSMC's priority is cost control and yield stability for its customers, and it considers the ~$400 million per-tool price tag unjustified for its near-term roadmap .

TSMC has already received an R&D High-NA system (EXE:5000) and has begun developing lithography processes for High-NA scanners in 2025, but it is in no rush to deploy them in production .

How the Delays Affect ASML

ASML's overall revenue outlook remains strong. The company reported €32.7 billion in total net sales for 2025, with a Q4 2025 record of €9.7 billion, and ended the year with a €38.8 billion order backlog . For 2026, ASML has a target of over 60 Low-NA EUV shipments — approximately 25% more than 2025 levels — and plans to increase overall capacity by 30% per year for the next two years to meet surging AI-chip demand .

The push-out of High-NA volume orders from both TSMC and Samsung to the late 2020s / 2030 means High-NA will ramp more slowly than earlier market expectations. Analysts note that TSMC's deferral specifically "weighs on ASML's outlook" for the high-end segment . Each deferred purchase frees up roughly €350–400 million for a customer, but for ASML it means the billions in expected High-NA revenue will take longer to materialize .

ASML is managing the slower High-NA ramp by focusing on the next-gen EXE:5200B system (first shipped in Q2 2025) and relying on Intel — and to a lesser extent SK hynix for DRAM — as the lead High-NA customers in the near term . The company also shipped a total of eight High-NA systems through early 2026, according to its Q4 2025 press conference .

Summary of High-NA EUV Timelines

The Bottom Line

Intel's early lead with High-NA EUV is real and tangible: it is the only company today shipping a high-volume logic product made with the tool. Samsung and TSMC are both taking a wait-and-see approach, prioritizing cost and yield over being first to market. For ASML, this means the High-NA ramp will be gradual rather than explosive, but the company's overall business remains robust thanks to insatiable demand for its mature Low-NA EUV and DUV tools driven by AI-chip manufacturing.