Innodisk's DDR5 MRDIMM Gen2 is built around two new silicon components — an MRCD (Multiplexed Registering Clock Driver) and ten MDBs (Multiplexed Data Buffers) per module — that enable simultaneous access to two memory ranks, effectively doubling the data rate per channel .
The module was previously shown at Computex 2026 (June) and Embedded World 2026 (March), but the formal launch and sampling schedule were confirmed in late July .
The fundamental architectural difference is that MRDIMM multiplexes data from two ranks through MRCD and MDB components, rather than relying solely on a higher pin clock rate. This approach reduces memory controller load and improves effective latency compared to simply scaling frequency on a standard RDIMM design .
| Metric | Innodisk DDR5 MRDIMM Gen2 | Typical DDR5 RDIMM (previous gen) |
|---|---|---|
| Data rate | 12,800 MT/s | 8,000 MT/s (high-end) / 6,400 MT/s (standard) |
| Bandwidth vs. 8000 MT/s RDIMM | ~60% higher | Baseline |
| Architecture | Multiplexed dual-rank access via MRCD + MDB | Single-rank access per channel via standard RCD |
| Pin/slot compatibility | 287-pin — fits DDR5 RDIMM slots | 288-pin standard |
This launch aligns with JEDEC's finalization of the DDR5 MRDIMM Gen2 standard, which targets 12,800 MT/s as the defined speed for next-generation server memory . The JEDEC roadmap already points to MRDIMM Gen3 targeting 17,600 MT/s . The driving force is the insatiable bandwidth demand from AI inference and training — large language models (LLMs), generative AI, and robotics — where memory bandwidth directly constrains token generation throughput .
Innodisk positions this module within its "AI Memory Series," alongside CXL memory modules and LPCAMM2, targeting both data-center servers and edge AI systems that need high-bandwidth memory in a standard DDR5 socket without migrating to entirely new platforms . Rambus, a key chipset supplier, has also confirmed its MRDIMM chipset components for the 12,800 MT/s tier, reinforcing the ecosystem's readiness .